Other Parts Discussed in Thread: LMH0340, LMH0341, LMH0070
I've compiled the Altera fpga code ( NSM_SINGLELINK ) but it's made for a CycloneIII and I've got a NAX10 so I don't know if I've mistranslated the PLL or desializer or something... OR if there's a trick to making the LMH034- based fpga code work with the LMH0071.
I CAN FIND NO INFORMATION ON HOW THE 5-BIT DATA BUS ( lvdsTX[4:0] is to be compiled into the 20-bit pre-descrambler bus.
I suppose I could trial and error the 5-bit code order but it would help if I knew something about the 5-bt words inter-relationship
Do SYMBOL N and SYMBIOL N + 1 combine into a single 10 bit word ?
Or do SYMBOL N+1 and SYMBIOL N+2 combine into a single 10 bit word ?
Where does the upper 10 bits come from in the LMH0071 ?
There only 10 bits of data coming across the bus at 27MHZ yet the 'ipt_rx_io_altera" module puts out a 20 bit bus !!
Is the upper 10-bit word a dulicate?
is it needed?
Is there ANY DOCUMENTATION ANYWHERE WHICH ACTUALLY ANSWERS THESE VERY BASIC QUESTIONS ????
Thanks