Hello Ari,
You mean in the clocktree tool ? Can you share the screenshot of the change ?
Also if you changed it in the clocktreetool did you enable device support ?
Thanks!
Hello Rafael,
I have noted your question.
For information about prescaler values and frequency fed to the M4F Timers, I would highly encourage you to go through the tool which TI provides, namely Clock Tree Tool.
For AM62x you can find the clock tree…
Other Parts Discussed in Thread: CLOCKTREETOOL Hi, Experts
We are considering how to operate GPMC_CLK=100MHz while keeping the DSP/ARM clock at 1000Mhz using ClockTreeTool. The current design is to input 24MHz to SYSOSC and SYSCLK1=1000MHz with PLL_MAIN…
Hi Spencer,
In your SYSCONFIG screenshot, it seems you are not using the AM6X Clock Tree software product. The default software product helps to configure the peripherals and the device settings, but does not show the clock tree diagram. To show the clock…
Hi Zenz,
Zenz Beneens said: Or is the higher consumption due to losses in the PMIC?
There has not been any analysis on this.
Zenz Beneens said: Do the dual core ICs have a lower consumption than a quad core with 2 cores disabled?
In theory, yes since the…
Hi Daisuke-san,
SERDESn_REFCLK_x can definitely take in an input, but I will need to check if it can support outputting a REFCLK. For PCIe in our SDK, outputting the REFCLK comes not from SERDESn_REFCLK_x, but instead, it comes from PCIE_REFCLKx_OUT if…
Hello Sakai
Thank you.
Ryosuke Sakai said: In EMC, a frequency component that is 7 times OSC0_IN (25MHz) is detected.
Do you have the Ethernet interface or any other peripheral working at 25M?
Ryosuke Sakai said: Is it okay to consider Interface clock…
Part Number: 66AK2G02 Hello,
I am attempting to use the clock tree tool (CTT) on my Ubuntu 16.04LTS machine, but have had no luck getting it to run. When I attempt to run the JAR using the following command:
java -jar CTT-66AKG0x_SR1.0-v1.0.0.1.jar
I…
Hi Shai, Short answer is no the GPMC cannot take in an external clock source as its reference clock. Its only clock source comes through the core PLL and HSDIVIDER. OSC0 is limited to 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz. The PLL could be bypassed, but…
Hello Aaron,
I went looking through the watchdog clock sources today.
Summary
Do you have a 32kHz oscillator connected to input WKUP_LFOSC0? If so, please verify that the watchdog is getting sourced by that clock source. If not, please show me which clock…