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Original question:

THS3491: Zol test and parasitic capacitance of noninverting terminal questions

THS3491: TINA simulation questions

Owen Yan
Intellectual 1820 points
Part Number: THS3491

Hi Team,

Michael Steffes provided the following method to simulate open loop gain and feedback transimpedance of CFA.

But I can't figure out why the next circuit couldn't be used.

B R,

Owen Yan

  • 0
    Guru 140200 points

    Hi Owen,

    you must provide a DC current path for the input bias currents of THS3491. And a current source by definition has an infinite source resistance. Because of this a simple current source instead of Michael's biasing scheme will not do the trick.

    Kai

  • 0
    Guru 47495 points

    hey Owen, I was starting to look at this, having some trouble with the product folder models, The RGT does not want to operate correctly and DDA looks better, but needed some tricks to get rid of numerical chatter - Anyway, the 1st thing you need to do to run a loop gain sim is to extract the open loop inverting impedance. This set up does that, where the feedback Inductor opens up on the 1st AC step and the large C shorts out. What is there at DC closes the loop and finds a good DC operating point. So this is showing 23.6dBohms at DC (15ohms)with an inductive zero at 500MHz. That implies a series L of 4.8nH.

    Then what you need to do is add this impedance at the summing junction in a LG sim with the sense current meter on the other side of that. Here that simulation is showing about 134MHz LG=0dB crossover with 78deg phase margin - you have scaled the R's up which will overcompensate the design. 

    Here is a V9 file of this, but again I had trouble getting this to run and used some V11 features you may not have, 

    THS3491 DDA 2018 model LG test.TSC

  • 0 in reply to kai klaas69
    TI__Intellectual 1820 points

    Hi Kai,

    I'm so sorry that I can't understand the path of input bias currents. Could you please draw the path for me with the different methods. Thanks for your help!

    B R,

    Owen Yan

  • 0 in reply to Michael Steffes
    TI__Intellectual 1820 points

    Hi Michael,

    Yes you are right. In your article, the CFA with a closed loop buffer has bigger parasitic inductance. And I wonder, if I want to simulate CFA, do I need to extract the open loop inverting impedance even it's a open loop buffer? 

    B R,

    Owen Yan

  • +1 in reply to Owen Yan
    Guru 140200 points

    Hi Owen,

    as you can see from the

    THS3491DDA TINA-TI Reference Design (Rev. A)

    parasitic capacitances of layout will play an enormous role on bandwidth. The same is true for the unavoidable self capacitance of SMD resistors. Because of this the simluation with ideal layout and ideal resistors might not give the higest bandwidth Relaxed

    What circuit do you want to simulate? The inverting or non-inverting amplifier?

    Kai

  • 0 in reply to Owen Yan
    Guru 47495 points

    Since we are working with sim models, it is best to extract what is in the model for the part in question, as I did above. 

  • 0 in reply to Michael Steffes
    TI__Intellectual 1820 points

    Hi Michael,

    How did this picture drawn? It's from a real board in the lab or from sim?

  • +1 in reply to Owen Yan
    Guru 47495 points

    This was measured using the eval board and a network analyzer - with that data then taken into Excel to normalize the plotted data. The peaking gain of 2 plot seems to be hitting a slew limit with that discontinuity

  • 0 in reply to Michael Steffes
    TI__Intellectual 1820 points

    Hi Michael,

    The CFA with internal closed loop buffer has a bigger parasitic inductance which could lead to the gain peaking. But THS3491 with open loop buffer, the gain peaking is caused by hitting a slew limit. Am I right? And as for the black thread, the feedback transimpedance(FT)=2*15+2100=2130Ω, which is biggest and should have the smallest BW, means that the point of F-3dB should be on the left of others, why it's not?

    Thanks for your help!

    B R,

    Owen Yan

  • 0 in reply to Owen Yan
    Guru 140200 points

    Hi Owen,

    Owen Yan said:
    I'm so sorry that I can't understand the path of input bias currents. Could you please draw the path for me with the different methods.

    The input bias currents are flowing this way:

    Keep in mind that the component in the feedback loop must be an inductance. So your R2 in your very first picture should actually be an inductance and not a resistor Relaxed

    Kai