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LF198QML: How to design Sample & Hold chip Guard Ring?

Woo Huiseung
Prodigy 30 points
Part Number: LF198QML

Above the picture, the Green pattern is located on the PCB TOP Layer, and the Red pattern is located on the PCB Bottom layer, which makes them look overlapped with each other.

U43 is an LF198 (Sample & Hold) chip, pin(5) is an output pin, pin(6) is a hold cap pin, and C48 is a Hold capacitor.

I'm going to design the Guard Ring for the Sample & Hold chip, but is it problem when applying the Guard Ring as shown in the picture above??

If it is a wrong Guard Ring pattern design, Please check how the guard ring should be applied. 

Thanks

best regards.

  • 0
    TI__Guru* 93105 points

    Hello Woo,

    Here is a comment about guard rings from one of our legacy, ultralow input current op amps:

    A “guard” pattern should completely surround the high impedance input leads and should be connected to a low impedance point which is at the signal input potential.
    In the case of the LF198QML it appears that you are attempting to minimize leakage currents that could impact the hold capacitor that connects to pin 6. If that is indeed what you are attempting to do, datasheet Figure 24 shows the guarding technique for the hold capacitor pin. The hold capacitor input pin 6 is the high impedance input lead in this case, which is surrounded by the low impedance output presented by pin 5.
    Regards, Thomas
    Precision Amplifiers Applications Engineering