LMP7704-SP: TINA Model from SNOAA75A (Space-Grade, 100-krad, 125-kHz Photodiode TIA Circuit)

Hey Daniel, I had this set up from a recent question, however, 

I reviewed that app brief - very good, but in any LG phase margin test we need a load defined to be sure we are not missing anything. I suppose in the app note, that was undefined. 

It would be better for you to have load in those sims, even if only the RC of the next stage. I will go on with what I have. 

Ok, working from the 2021 model update, here is a LG sim set up a little better and including the parasitic input C for the LMP7704 which is quite high, 64 degrees is very good, but can degrade quickly with parasitic C load. 

And here is this file in TINA V9

LMP7704SP Zt LG test.TSC

And then your closed loop sim, very nice flat 188kHz design, 

And this sim file, 

LMP7704SP Zt closed loop.TSC

Yes, using two different methods I can confirm that the circuit seems pretty stable with 64 degrees phase margin - see below.

LMP7704-SP Photodiode TIA.TSC

Michael,

An open-loop output impedance of LMP7704-SP looks pretty typical for RRIO CMOS op amp - see below.

You bet Daniel, 

Well Marek, I need to find out what I was doing wrong  on the Zol sim, 

I did illustrate a more extreme miss using the OPA837 with that output injection technique in this article, along with a number of other gotcha's in legacy literature

https://www.planetanalog.com/stability-issues-for-high-speed-amplifiers-introductory-background-and-improved-analysis-insight-5/

Ok, I added that 99.97MF cap on the inverting input to ground and things cleared up a lot, I think this is about what you show with numerical chatter up higher F. I am using the Dec2021 model update and this does look very reasonable, 

LMP7704SP Zol test.TSC

Yes, that's pretty close - other than at high frequency.

Hi Daniel,

and I get this result for the phase stability analysis:

daniel_lmp7704.TSC

Kai

Yes Kai, I think this is a more thorough approach, and I use it sometimes,.You had guessed on the Cdiff to Ccm split I think, if that 3pF  Ccm and 25pFis in the datasheet I cannot find it. For the simple Zt stage with V+ grounded, we usually just use a single Ccm + Cdiff for design. 

Sadly, this level of accurate detail is missing from a lot of datasheets - We had found a lot of parts with bad numbers here, where most of the time the Ccm is >> Cdiff in the CMOS input stages. I will try this with 20pF Ccm and 5pF Cdiff. seeing 64deg now, still real good and basically this design is very stable, all this later discussion is methology pitfalls. 

Hi Mic hael,

the 25pF is mentioned in section 7.3.4 of datasheet. And when you open ths Spice model you will find this:

* e. DIFFERENTIAL INPUT IMPEDANCE (Zid)
* f. COMMON-MODE INPUT IMPEDANCE (Zic)

And later in the model you will find:

C_C_COM0 ESDP MID 3P
C_C_COM1 MID ESDN 3P
C_C_DIFF ESDN ESDP 25P

Kai

Thanks Kai, the next obvious question is if this is correct. We were finding several that had this kind of split, that, in fact, were higher on the Ccm. Easy bench test, set up for a unity gain follower with 10kohm series input and check the output bandwidth being limited by either 3pF or something higher.

And Kai, I was looking at the is relatively new chopper amp (ADA4522) for CMRR reasons, and noticed the input C's look like what I would expect in a low input noise CMOS device. That 130dB min CMRR over 0 to3.5V input CM span maps to a 0.2uV vos shift (perhaps, I think this is actually a gain term for the CM to input Vos terms).