OPA810: power solution for opa810, ths4551 and adc

Hello Liping,

I have a few observations to share with you:

#1: Though I do not support ADC products outright, I can tell you that 4.5V for AVDD is the exact minimum recommended operating supply voltage for using high-speed mode.

#2: If you power the OPA810 on either +/- 5V or +/-4.5V, the rail to rail input/output will allow enough headroom for a 2.7-4.2V input signal (and the output signal, since the amplifier is in a gain of 1 configuration.  Please note the input and output range characteristics in Table 7.5 of the datasheet.

#3: The THS4551 operates on single supply; this device does not have rail to rail inputs.  As such, the maximum allowable input voltage on a 5V supply is 3.9V.  Your input signal would clip and exceed the maximum allowable input signal on the THS4551.  For a 4.5V supply. this value would be even lower.  Please refer to Table 7.5, second page, under "Input" of the THS4551 datasheet.  The spec notes that the input limitation is Vs+ - 1.1V.  

With the current setup, the THS4551 will not be able to handle the full-scale input of the 4.2V input signal coming through the OPA810 circuits.  Please examine your input signal requirements and see if you can utilize a lower voltage input signal, or perhaps attenuate the input to the THS4551 slightly.  The THS4551 does have rail to rail outputs, which can reach up to 4.8V on a 5V supply.

If you can tighten your input signal range, your two schema are viable.  Considering the input limitations of the THS4551, the 5V power solution (solution #1) is preferable.  

Best,

Alec

Hello Liping,

I do think the first power solution is viable, but it would require a decrease in the input signal level.  As you stated, your input signal is 2.7V - 4.2V.  A decrease of 0.4V would result in a 2.3V - 3.8V input signal.  The voltage peak of 3.8 is below the 3.9 required by a THS4551 on 5V supply.  The shift of the lower voltage threshold to 2.3V would not violate any input or output limitations on the negative rail, as Vs- = GND.  

I think a small DC offset would be the quickest way to amend the mismatch of input signal to common mode input range.  If changing the input signal is not an option, you would need to operate with 0.3V higher supply on the THS4551 for operation at 25C.  A 5.3V supply would result in a maximum input voltage of 4.2, which aligns with your signal needs.  

Another important point is that the headroom increases if you are operating over -40C to 85C temperature range, in which case the maximum allowable input voltage is 1.2V from the power rail.  This would require a 5.4V supply on the THS4551, which is the maximum recommended operating condition.  The absolute maximum of the THS4551 is 5.5V.

In summary, you can either raise the supply voltage on the THS4551, or decrease your maximum input signal voltage by DC offset or attenuation.  

Best,

Alec

Hello Liping,

I understand better now; thank you for being patient with me and my advice.  I appreciate your consideration on following the recommended operating conditions for the THS4551.

I did review your power solution; I did not see any issues or areas of concern from my perspective.  The typical (TYP) values for quiescent current (Iq) for the THS4551 and OPA810 are 45mA (THS4551) and 3.7mA (x2) for the two channels of the OPA810.  This results in the two amplifier solution having a net quiescent current draw of 52.4mA.  The OPA810 can output 75mA current, and the THS4551 can drive a maximum of 65mA output.  After considering the sum of these currents, and acknowledging a more detailed power consumption analysis could be performed on the entire circuit if needed, the amplifier section can likely draw up to 200mA.  As this sequence of OPA810 -> THS4551 -> ADC is repeated for a total of 4 iterations, and the ADC power consumption is not included in my calculations, this sub-circuit can draw around 1A at worst-case/highest power draw.  Please check if the power consumption (in mW) of the ADC is acceptable for your design (I do not see an issue).  As the batter+charger & next circuit TPS61288 result in a maximum output current of 4A, I do believe the amplifier/ADC section of the signal chain can be adequately supplied.

You also have another 4x OPA810, which would draw up to 100mA x4, so 400mA total.  These numbers are at highest recommended current being driven out of these amplifier parts; the actual power draw and current driven would be lower.

I would recommend checking the power consumption of the FPGA/digital side of your design; those devices should have listed current consumption or overall power consumption specifications.

Overall I think your design is good from an amplifiers perspective; please ask your question again in the power forum if you have specific power sequencing questions.

Good work with your design & thank you for asking good questions.

Best,

Alec