LMP7721: Transimpedance amplifier - Question about layout, guard and copper pours

Alan Islas

Part Number: LMP7721
Other Parts Discussed in Thread: OPA928, OPA928EVM

Hi,

I'm working on a sensor application using a photodiode connected to a transimpedance amplifier with a 5 Gigaohm feedback resistor.

Read Paul Grohe's 2011 series of articles "Design femtoampere circuits with low leakage" but I still would like to confirm my approach.

Basically I'd like to get an opinion on my layout please. The help is very much appreciated.

Tied the Guard to GND since that is the same potential as the +IN input. See Paul's response to a similar question here (from 9 years ago!):

https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/403092/lmp7721-inverting-trans-impedance-amplifier-and-guarding

Connected the +IN input to the guard and whole thing to the ground plane using a single point. See image below.

Other precautions were to remove the copper pour under the sensitive area on all layers (this is a 4 layer board) and also remove the soldermask on the critical area on both sides:

The photodiode has a round footprint with through hole pins, only two of them active (anode and cathode). I removed the plating and pads from the pins adjacent to active pins, to avoid bring noise in (planning to cut those unused pins). For the cathode pin I removed the plating and just left the pad on the top side, where it will be soldered. That way the pin is not soldered across the hole plating and to the other side, potentially picking up noise from there. For the anode pin I do need to take a signal out on the secondary, so I left the plating and top and bottom pads.

Trace widths for critical signals is 8 mils. Added the pads for feedback capacitor (0805) that I may or may not populate, based on testing results. Found ceramic capacitors with an insulation resistance of 50 Gohms, so substantially higher than the 5 Gohm of the feedback resistor. The output goes to a second stage, another op amp in voltage amplifier configuration. Around the whole thing there is a metal shield enclosure, placed along the thick GND traces.

Thanks!

over 1 year ago

0 Zach Olson over 1 year ago

TI__Genius 10565 points

Hi Alan,

Paul Grohe's articles are a great reference for high-impedance TIA circuits, I'm glad you found them useful.

I have a few notes about your layout. See below.

1.) Connected the +IN input to the guard and whole thing to the ground plane using a single point.

I recommend making these guard traces significantly wider. The guard should be very low-impedance. Long, thin traces such as this will have parasitic resistance and inductance that is undesirable. Adding additional ground connections to the guard will also reduce the impedance, as opposed to a single ground via connection.

2.) Other precautions were to remove the copper pour under the sensitive area on all layers (this is a 4 layer board)

What potential is the copper pour that was removed?

It looks like the copper pour is ground potential, which is already directly connected to your guard trace. By removing the ground pour, you are essentially removing additional guard copper. Including the ground copper on the internal and/or bottom layers will protect from current leaking vertically through the board from other layers. This will also provide some EMI shielding for your sensitive traces.

If the copper pour is some other potential such as power supply, it should be removed as shown.

3.) and also remove the soldermask on the critical area on both sides.

This is good. Any sensitive traces that are exposed on either side of the board should be guarded and the solder mask should be removed from within the guarded area. The solder mask should be removed from the guard traces as well. I don't see the bottom-side guard in these images. The through-hole cathode pin should be guarded on the bottom-side of the board, even if the hole plating is removed.

4.) For the cathode pin I removed the plating and just left the pad on the top side, where it will be soldered.

This is an interesting idea. I would like to learn how effective this is in reducing the noise coupling. It is typical is to use grounded RF shields which will fully enclose any exposed sensitive nodes. Unfortunately, the through-hole nature of your photodiode would require you to place a shield on both sides of your PCB, or to place the entire test fixture within a shielded enclosure during operation.

I am concerned about the mechanical connection of your photodiode to the annular ring. Small copper pads like this can delaminate from the PCB very easily. I'm not sure how well a large through-hole component can rely on this thin copper weight for its mechanical stability. It is up to you how confident your are in this assembly process, but I would think that the risk of assembly failure outweighs the potential noise reduction.

5.) For the anode pin I do need to take a signal out on the secondary, so I left the plating and top and bottom pads.

What is this trace coming from the anode pin connected to? Is this a high-impedance traces as well? Typically the anode of a photodiode is biased to some low-impedance potential, either ground or some negative voltage to reverse-bias the diode.

If this node is not a sensitive high-impedance trace, it should not be located within the guard area. Any voltage potentials or noise on this node will cause leakage currents within the guard area that are not protected from leaking into your sensitive traces. You may reroute your guard traces to separate this pin from the guard area.

6.) Added the pads for feedback capacitor (0805) that I may or may not populate, based on testing results. Found ceramic capacitors with an insulation resistance of 50 Gohms, so substantially higher than the 5 Gohm of the feedback resistor.

A TIA configuration with a 5 GΩ feedback resistor is likely susceptible to stability issues without appropriate compensation. With such a high impedance resistor, it is possible that parasitic capacitance from the layout could be enough to stabilize the amplifier. However, if you notice oscillations or other unexpected operation I would suggest populating the compensation capacitor. This will feedback capacitor will also help reduce the noise.

I will refer you to the OPA928 datasheet for more information on femtoampere-performance TIA circuits. Section 8.4 has layout guidelines and best practices, as well as some example layouts. OPA928 is a new femtoampere input bias current device that you may consider for your circuit as an upgrade to LMP7721.

https://www.ti.com/product/OPA928

https://www.ti.com/lit/ds/symlink/opa928.pdf?ts=1694718820289&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FOPA928

The OPA928EVM has a TIA circuit with the guard copper connected directly to ground, similar to your design. The layout shown in the OPA928EVM User's Guide uses many of the techniques I described above such as wide guard traces with multiple ground-via connections, three-dimensional guarding, top and bottom shielding, etc.

https://www.ti.com/tool/OPA928EVM?keyMatch=&tisearch=search-everything&usecase=hardware

https://www.ti.com/lit/ug/sbou282a/sbou282a.pdf?ts=1694727707631&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FOPA928

Please let me know if you have any additional questions.

Best Regards,

Zach

0 Alan Islas over 1 year ago in reply to Zach Olson

Prodigy 60 points

Hi Zach, thank you very much for your quick and very detailed answer! It is appreciated very much! Also for brining to my attention the new OPA928.

Please see my responses below.

1.) Connected the +IN input to the guard and whole thing to the ground plane using a single point.

Made the guard trace thicker where possible. However, I'm worried about the guard trace being too close to the pads. And this might be a fundamental misunderstanding on my part, but could there be some small level of capacitive coupling if it gets too close?

I went with the single point connection as a kind of "star ground" approach, and here again I'm unsure. Added a second via to the ground plane, two next to each other, as a compromise. I hesitate to connect the guard, and in this case the sensitive input, to several points of the ground plane. Could that cause ground loops if those points happen to be at slightly different potentials? I'd like to add that is application is a low frequency application. I saw a lot of discussion in audio application forums about how effective and appropriate is a ground plane for lower frequencies. For example:

"When the frequency is so low that return currents cannot follow signal currents in a ground plane (because the plane is thinner than the skin depth), it is more effective to force the return current to follow the signal current by using differential traces than it is to rely on the ground plane. The magnetic field radiated with a ground plane can actually be larger because the signal and return currents take different paths and form a loop.

So I see ground plane usage on audio circuits as being distinct from RF where the skin depth is well above the plane thickness. If we want to incorporate ground planes into audio circuits, we need to make sure the return current follows the signal current even at frequencies where the ground plane is ineffective (which is everything below at least 5KHz)."
https://www.diyaudio.com/community/threads/audio-pcb-layout-techniques.235384/page-6

2.) Other precautions were to remove the copper pour under the sensitive area on all layers (this is a 4 layer board)
The copper pours in layers 2 and 4 (bottom side) is nominally at ground potential. I actually had an earlier version of this board with the internal and bottom side copper under the sensitive area, connected to the guard, for exactly the same reasoning you provide. That board did not work, however, I'm not sure if it was because of that. Again, I'm worried there could be capacitive coupling to the ground planes, if I left the copper underneath. Also worried there might be other current returns from other circuits in the boards passing under my sensitive area and coupling into the input, at very low levels, but affecting due to the low current of the design. Not sure if this makes sense. This board is a remake of an older board with a different phototube. That one works, it is only two layers and there are no copper pours in the critical area. I thought the safest approach in this latest attempt is to try to stay closer to the original design.

3.) and also remove the soldermask on the critical area on both sides.

Showing bottom side with added guard trace and soldermask removal (pink).

4.) For the cathode pin I removed the plating and just left the pad on the top side, where it will be soldered.

About the mechanical stability, most of the unused pins will be fully soldered. I put back the plating and pads on pin 9, which is outside the guard.
So I removed the plating and pads completely from three pins, left just the top pad with no plating on the cathode pin, and left 8 pins fully connected, 7 unused and the anode. Should be enough.

5.) For the anode pin I do need to take a signal out on the secondary, so I left the plating and top and bottom pads.

Yes, it is connected to a biasing voltage. Moved it out of the guard on both sides of the board.

0 Zach Olson over 1 year ago in reply to Alan Islas

TI__Genius 10565 points

Hi Alan,

See my responses below.

1.) I'm worried about the guard trace being too close to the pads. And this might be a fundamental misunderstanding on my part, but could there be some small level of capacitive coupling if it gets too close?

You are correct, any two conductors that are separated by an insulator will exhibit some amount of capacitance, in fact this is the definition of a capacitor. The parasitic capacitance of your guard traces will be negligible, especially when operating at such low frequencies. I believe the OPA928 layout examples have a clearance of 20-mil from guard to traces. If you are concerned with capacitive coupling, you may expand this to 40-mil.

2.) I hesitate to connect the guard, and in this case the sensitive input, to several points of the ground plane. Could that cause ground loops if those points happen to be at slightly different potentials? "When the frequency is so low that return currents cannot follow signal currents...

The return current will always follow the lowest impedance path back to the source. At DC and low frequencies, this will be the shortest direct path (lowest resistance). At high frequencies, the impedance is dominated by inductance and therefore the current will follow the path with the smallest loop area (lowest inductance). At "medium" frequencies, the current will return through both paths as the resistive and inductive contributions to the overall impedance become equal (think of the current path through two resistors in parallel). These "medium" frequencies can actually be quite high, perhaps 800kHz. This article is a great reference on this topic: https://www.ewh.ieee.org/soc/emcs/acstrial/newsletters/spring08/design_tips.pdf

The purpose of the guard is to present a low-impedance path equipotential to the input traces. Current that is leaking toward the high impedance input path prefers the low-impedance guard path and will be shunted away from the signal path. Current flowing between the input and guard traces is negligible because both traces are ideally at the same potential, in this case Vcm = 0V. The leakage current paths are a different consideration than the signal current return path. The leakage currents are generated from various voltages present in your PCB, whereas the signal current is generated by your signal source.

A solid ground plane with many via connections provides a very low-impedance current return path. The lower the impedance of the return path, the lower any voltage differentials on the ground path will become (V=IR), and therefore the less susceptible to ground loops developing. You are correct that because your guard is connected to the analog ground of the circuit, special attention must be given to ground return paths from elsewhere in the PCB, such as digital or power supply current return paths. Current returns from elsewhere in the PCB can be prevented from crossing through your guard copper with the understanding that those currents will take the lowest-impedance path back to their source as well. In the OPA928EVM, I provided my solid-state relays with their own dedicated current return trace to ensure this current did not cross the guard.

If you cannot control the return paths from elsewhere in the circuit, connecting your guard to a single point may be acceptable, however you will not benefit from the three-dimensional guarding that the additional vias will provide. Any voltages present on internal routing or vias (such as your anode bias) may generate leakage currents that flow diagonally through the PCB into your signal traces.

3.) I actually had an earlier version of this board with the internal and bottom side copper under the sensitive area, connected to the guard, for exactly the same reasoning you provide. That board did not work... I'm worried there could be capacitive coupling to the ground planes, if I left the copper underneath. Also worried there might be other current returns from other circuits in the boards passing under my sensitive area and coupling into the input, at very low levels

What do you mean the board did not work? Did you measure large amounts of leakage current? Was the amplifier stable? Did you populate a compensation capacitor in parallel with the 5GΩ resistor? Were the boards thoroughly cleaned and baked after assembly?

As mentioned above, this ground plane will add some parasitic capacitance. However, at such low speeds this parasitic capacitance should be negligible. You are more much likely to benefit from the vertically guarding against leakage currents from other PCB layers than you are to suffer from effects of parasitic capacitance.

4.) Showing bottom side with added guard trace and soldermask removal (pink).

What is this via (circled in red) connected to? Is this a high-impedance node? Is this node guarded on the top side as well? My understanding was that the only high-impedance through-hole you have is the cathode pin? If this is the case, only the cathode pin should be guarded. You may even consider removing the two unused vias next to the cathode pin, since you plan on removing these pins from the diode as well.

If you can provide a schematic, it will help me to better understand which nodes in your circuit require guarding and which nodes do not.

Also, what is this via (circled in blue) connected to? Is this a high-impedance node? It is not guarded on the bottom layer.

If this is via is connected to any potential other than ground, it will need to be guarded as shown below.

Regards,

Zach

0 Alan Islas over 1 year ago in reply to Zach Olson

Prodigy 60 points

Hi Zach, thanks again for the in depth support and sharing your expertise, it is truly appreciated!

"If you are concerned with capacitive coupling, you may expand this to 40-mil."
Tried to compromise between guard trace thickness and proximity to the inputs:

2) and 3) 3D guarding

"If you cannot control the return paths from elsewhere in the circuit, connecting your guard to a single point may be acceptable, however you will not benefit from the three-dimensional guarding that the additional vias will provide. Any voltages present on internal routing or vias (such as your anode bias) may generate leakage currents that flow diagonally through the PCB into your signal traces."

To be honest my previous version had other issues so I did not do a very in-depth troubleshooting, too many confounding variables.
So the approach for this version is to stay closer to the original 2-layer design with the obsolete photodiode, confining the critical area to the top layer as much as possible, as if it were wired above the board surface. So I've removed everything from the internal layers and moved away the vias that could potentially interfere. That way, the potential leakage sources are minimized. Now that I've moved the anode pin out of the guard I removed the plating and bottom layer pad, and routed on the top layer, where the guard can be effective, only placing a via away from the critical area. See below:

4.) Showing bottom side with added guard trace and soldermask removal (pink).

"What is this via (circled in red) connected to? Is this a high-impedance node? Is this node guarded on the top side as well?"

This design modulates the signal to a lower frequency, using the photodiode as a mixer, with a signal on the anode mixing with the transmitter LED frequency. The via you mentioned is the through hole pin of a variable capacitor used to any AC bias that could saturate the amplifier. Something like shown below.

I'm not sure what the previous designer did it like that, with the variable capacitor pin outside the guard, even when it is connected to the input. It is located so far away because the capacitor needs to be adjusted manually. The resistor you see at the end of the long trace is a zero ohm jumper used to get the signal into the guard.

Now I think the capacitor pin and trace should all be inside the guard, both on the top and bottom sides. Do you agree?

"Also, what is this via (circled in blue) connected to? Is this a high-impedance node? It is not guarded on the bottom layer. "

The LMP7721 is configured as a composite amplifier with another op-amp, as shown in the LTspice schematic below. Didn't include the bypass or feedback capacitors. The via you circled takes the right side of the 5G resistor to the composite output. The second op amp is outside the guard. So I think the guarding you suggested (across the middle of the 5G Rf resistor) applies to this situation, right?

0 Zach Olson over 1 year ago in reply to Alan Islas

TI__Genius 10565 points

Hi Alan,

No problem. I am happy to support a femtoampere-level design, especially an interesting one like this!

I have a few more notes on your design, see below.

1.) Now I think the capacitor pin and trace should all be inside the guard, both on the top and bottom sides. Do you agree?

Yes, this is correct. Any node that is directly connected to the inverting input (high impedance node) must be within the guard area. I would suggest the guard is expanded to the middle layers as well because the capacitor pin is coming in on a via. I believe you are not planning on removing the plating/bottom pad like you did with the cathode pin of your diode?

2.) So I've removed everything from the internal layers and moved away the vias that could potentially interfere. That way, the potential leakage sources are minimized. Now that I've moved the anode pin out of the guard I removed the plating and bottom layer pad, and routed on the top layer, where the guard can be effective, only placing a via away from the critical area.

I recommend adding some via fences to your guard, especially around your high-impedance through-holes. This extends your guard structure to the inner board layers and prevents leakage currents from finding diagonal paths through the board material into your sensitive nodes.

You may also add a guard via fence to protect against leakages from vias presenting other nodal voltages, such as the incoming power supply vias. Without a guard via fence, the power supply voltages present on the inner layers have a diagonal path to flow into the long sensitive trace coming from your variable capacitor. Image below is a quick rough-up, of course you will need to adjust the via-to-pad spacing appropriately.

3.) The LMP7721 is configured as a composite amplifier with another op-amp...The via you circled takes the right side of the 5G resistor to the composite output. The second op amp is outside the guard. So I think the guarding you suggested (across the middle of the 5G Rf resistor) applies to this situation, right?

Thanks for providing a schematic, this helps a lot. You are exactly correct. The input side of the 5G resistor is high impedance (connected to IN-), whereas the output side of the 5G resistor is low impedance as it is connected directly to the output of your composite amplifier. The guard should go straight through the center of the 5G resistor in order to guard the high-impedance input node from the low-impedance output node. Otherwise, the ~15V max output of your composite amplifier has an unguarded path to leak current back into the input node.

See examples from OPA928 datasheet:

4.)

I see that you are using a composite amplifier solution to increase the output swing to +/-15V while maintaining the femtoampere input performance of the LMP7721. The OPA928 was specifically designed for this purpose as it provides femtoampere-level performance in a 36V device. You will be able to greatly simplify your design and layout by using a single device instead of the composite solution shown. FYI, the preliminary version of the OPA928 datasheet shows 16V, but this will be updated to show 36V when the device is fully released.

You may also take advantage of the OPA928's integrated guard buffer to drive your guard traces to 0V. This will allow you to increase your guard area and add the appropriate fencing vias and 3D guarding scheme without introducing unwanted current return paths in your ground plane. The OPA928 guard pins (GRD) follow the voltage at the non-inverting input and present a low-impedance path for leakage currents to be shunted away from the sensitive nodes.

If you're interested in pursuing this solution just let me know and I can get you in touch with our field support team. They will be able to provide you with samples or even an evaluation module.

Best Regards,

Zach

0 Alan Islas over 1 year ago in reply to Zach Olson

Prodigy 60 points

Hi Zach,

Thanks again for the help. I've implemented the recommendations and will be ordering the board soon to be tested.

Also, I'm very interested in the OPA928. It's too late for this particular design, but would definitely look into it for other applications in the near future.

Regards,
Alan

0 Zach Olson over 1 year ago in reply to Alan Islas

TI__Genius 10565 points

Hi Alan,

Sounds good, I'll go ahead and close this thread for now. Feel free to reach out if you need further support on your design.

Best Regards,

Zach

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LMP7721: Transimpedance amplifier - Question about layout, guard and copper pours