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THS4222: THS4222 Issue

HD
Prodigy 160 points
Part Number: THS4222
Other Parts Discussed in Thread: TLC074, OPA2690, OPA2890

Hi,

I need support about a simple circuit involving THS4222.

Attached you can see the circuit.

The input signal is a sinewave 3Vp 50Hz (0 offset), the output signal shows an offset (about 1.4V). Why?

What is the origin of this offset if the input signal has no offset?

I tried two simulators and the result is the same.

Thanks for your support.

Antonio

4705.Circuit.TSC

  • 0
    TI__Genius 12855 points

    Hello Antonio,

    I will investigate your circuit behavior.  Could you share the answers to the following questions?

    What is the desired gain of the amplifier?

    What is the frequency of the input signal?

    What is the amplitude of your required input signal?

    What is the output load of the amplifier circuit?

    As is it designed right now, your circuit is applying very high gain to a 3V amplitude signal (6Vpk-pk).  On a 10V split supply this circuit cannot support a gain of 2V/V, and especially not a high gain as you have the circuit configured.

    What is the desired goal or purpose of your circuit?  I can help debug and provide assistance.

    Best,

    Alec

  • 0 in reply to Alec Saebeler
    Prodigy 160 points

    Hi Alec,

    the design in question is not ours but from a customer who asked us to test the circuit.
    What we're trying to do is analyze it to then understand how to do the test... the circuit is more complex and it's consolidated in the sense that it's part of a product. I attach the most complete circuit section.
    Practically from what we understand there is a 230Vrms 50Hz sinusoidal signal that is attenuated and sent to an ADC... at the same time that signal is compared with a sinusoidal reference extracted from a PWM (generated by micro) to extract an error which is sent to the comparator window. All this is used to control the 230Vrms input signal via a microcontroller logic... In the end it is part of an inverter controller.
    Keep in mind that the circuit is already designed and consolidated... it's just a matter of understanding how it works and in particular when doing the simulations this offset came out from THS4222 which we don't understand if it is normal.

    I hope I have been clear in my fairly brief explanation.

    Antonio

    inv_mdl4.TSC

  • 0 in reply to HD
    TI__Genius 12855 points

    Hello Antonio,

    You are seeing the 1.55V offset due to the 3V DC bias present (V4 in TSC file).  This bias is set before the input to the TLC074, which is not AC-coupled and presents the same DC offset (bias) at the output.  

    Without this DC bias your output signal at V2 is a sinusoid with an amplitude of 811mV.  When the DC bias of 3V is present at V4, the resulting DC bias to the signal chain is 1.55V.  Your amplitude is still 811mV but off of a 1.55V offset, which results in the 2.36V peak seen in transient simulation.

    The THS4222 is operating exactly as intended with an attenuation of about -100V/V.  I think the issue is with the implementation or part selection of the TLC074 & the desired output signal level.

    Please see the attached simulation of the TLV074 circuit with the sinusoidal 50Hz 2.24 amplitude signal from the THS4222 at the input.  You should examine what the full-scale range and signal requirements of the ADC are for your design; you may be able to adjust your V4 voltage bias or change resistor values.

    tlc074_circuit.TSC

    You do also have some observable phase delay due to the filter implemented with TLC074.

    I hope this analysis helps!  Please let me know if you need additional assistance.

    Best,

    Alec

  • 0 in reply to Alec Saebeler
    Prodigy 160 points

    Hi Alec,

    what you say is clear but let's not lose the initial focus... what is the origin of the offset we see in the circuit involving only the THS4222? I attach the circuit simulation. As you can see there is an inherent offset to the simple circuit, beyond the bias from the previous stage.

    Best Regards,

    Antonio

    5432.Circuit.TSC

  • 0 in reply to HD
    TI__Genius 12855 points

    Hello Antonio,

    I am working to understand the second THS4222 circuit you shared.  What is the necessary attenuation for your application?  The device appears to simulate with no change in output when I vary Rf to change the gain.  There is some issue using the THS4222 here.

    I would like to know more about the reference sine wave modulated from PWM (is this also 3V 50Hz?).  Is the intention to use the THS4222 in an inverted summing configuration?

    I am confused by the C19 & R23 path in parallel with R22.  Is the signal at the C19 & R22 node the 3V 50Hz signal you described above?

    If you could elaborate on the desired input signal to this THS4222 and the desired output signal, I can help debug the application.  I do not know what function you want the THS4222 to perform or what signal is needed at the comparators which follow the second THS4222.

    I am not yet sure why in simulation there is the appearance of an offset.

    Best,

    Alec

  • 0 in reply to Alec Saebeler
    TI__Genius 12855 points

    Hello Antonio,

    I also tried swapping the OPA2690 and OPA2890 onto the TSC file you shared; the OPA2890 has similar offset while the OPA2690 has worse offset.  Between three parts, the OPA2690 has double or more input bias current.

    I think the high resistor value for R24 may be contributing to the offset observed in the circuit.  While the specified TYP value for input voltage offset affects the voltage in a straightforward way, input bias current multiplies with the feedback resistance to create an additional offset voltage.

    I am still looking into the cause for the offset with your application, but I would like to understand the function of the THS4222 labelled as "Comparison".  There are comparator ICs following this amplifier stage, so I would appreciate some context for the circuit.

    Best,

    Alec

  • 0 in reply to Alec Saebeler
    Prodigy 160 points

    Hello Alec,

    We don't know the attenuation... It is a consolidate circuit and it is working, we have onlty to test it so the values of the components are fixed. The circuit is used as a inverting summing configuration where the 3 signals are the AC source (scaled to about 3V), the reference 3V 50Hz sinewave (PWM modulated) generated by microcontroller (0-3.3V) and the same scaled AC signal that pass through RC (it seems as a practical differentiator). We suppose that the sinwave reference has to be generated with a 180 phase shift to have the subtraction in THS4222. If AC signal and reference have the same amplitude (error 0V) what survives is the only output of the differentiator that has that strange 'offset' and take the signal out of the window of the comparator. We think that the signal has to be in the window +0.9V/-0.9V if error is 0V.

    We tried other simulators and other opam... the offset is always present.

    Best,

    Antonio

  • 0 in reply to HD
    TI__Genius 12855 points

    Hello Antonio,

    Thank you for the update.  

    As I understand it, the total observed offset could be attributed to the sum of the following: input voltage offset, input bias current, and high noise gain.

    We have established the voltage offset observed in the circuit is not a behavior unique to the THS4222 but an overall circuit behavior depending on op-amp configuration & passive component selection.

    I will look at the theory and operation for the amplifier circuits.  In simulation, if you add a 100nF capacitor following the series 2.2kOhm load of the op-amp, is the resulting signal what you are expecting?

    You can certainly change the value of 4.7nF capacitor to scale the differentiated signal at the output of the simple RC filter.  When I ran simulation using two THS4222 amplifiers, one as a differentiator and one as an inverting summing, the result still showed the negative DC offset.  

    I do think the selection of Rf is a large contribution to the offset behavior.  

    Please consider changing the 4.7nF capacitor (or 1.5kOhm resistor) to increase the signal present at the inverting input to the amplifier.  I would recommend lowering the value of Rf and observing how the offset shifts closer to 0V as you lower the value.  

    If the signal is acceptable for the current design, I would recommend considering the affects of input bias current, resistor selection, and the trade-offs of the inverting scaling summing amplifier.

    Best,

    Alec