Tool/software:
I would like to expose the first few hundred bytes or so of the PCIE1_DAT1 area (address 0x05600000~) on the board side to the Root Complex side via PCIe.
I checked the Technical Reference Manual, and it states that access to BAR0 will see a group of registers in PCIe, no matter what address is set in IATU, as shown below.
Even if I set BAR0 on the Root Complex side, I cannot get the expected value and it is ALL 0xF.
Is there anything else I need to do to set BAR0 or anything else in this case?
Hi Masa,
DRA80XMEVM should be the alternative name for AM65 device. I would recommend looking through the Linux driver for how these registers are set up.
Specifically, it the driver in use should be the pcie-designware-host.c: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/pci/controller/dwc/pcie-designware-host.c?h=ti-linux-6.6.y#n396
And pci-keystone.c: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/pci/controller/dwc/pci-keystone.c?h=ti-linux-6.6.y#n298
Regards,
Takuma