Other Parts Discussed in Thread: C2000WARE
Tool/software:
HI I am trying to generate a 3 phase pwm signal with 120 degree phase difference, I am getting the 3 phase pwm signal 120 degree apart from the F28379D board on which the BOOSTXL-3PHGANINV is mouted by using the code attached, however, I am not getting anything on the inverter out VA, VB and VC, can someone help if there is anything wrong with my code or I am missing something. I applied a 12v battery across the inverte with no motr as i just want to see the current or voltage across the o/p terminals of the inverter.
//###########################################################################
//
// FILE: main.c
//
// TITLE: 3-Phase PWM Generation for F28379D with BOOSTXL-3PhGaNInv
//
// DESCRIPTION: This code generates 3-phase PWM signals with 50% duty cycle
// for the BOOSTXL-3PhGaNInv evaluation module using F28379D
//
//###########################################################################
#include "F28x_Project.h"
// Function Prototypes
void InitEPwm1(void);
void InitEPwm2(void);
void InitEPwm3(void);
void ConfigurePwmGpio(void);
void ConfigureADC(void);
interrupt void epwm1_isr(void);
// Global Variables
Uint16 EPwm1TimerIntCount;
Uint16 EPwm2TimerIntCount;
Uint16 EPwm3TimerIntCount;
// PWM Configuration Parameters
#define EPWM1_TIMER_TBPRD 2500 // PWM frequency = SYSCLK/(2*TBPRD) = 200MHz/(2*2500) = 40kHz
#define EPWM2_TIMER_TBPRD 2500 // Same period for all three phases
#define EPWM3_TIMER_TBPRD 2500
#define EPWM_CMP_UP 1875 // 75% duty cycle for demonstration
#define EPWM_CMP_DOWN 625 // 25% duty cycle for demonstration
// For 50% duty cycle, use TBPRD/2 = 1250
void main(void)
{
// Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
InitSysCtrl();
// Initialize GPIO
ConfigurePwmGpio();
// Clear all interrupts and initialize PIE vector table:
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
// Map ISR functions to PIE vector table
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
EDIS;
// Initialize PWM modules
InitEPwm1();
InitEPwm2();
InitEPwm3();
// Configure ADC for current sensing (optional)
ConfigureADC();
// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // EPWM1
PieCtrlRegs.PIEIER3.bit.INTx2 = 1; // EPWM2
PieCtrlRegs.PIEIER3.bit.INTx3 = 1; // EPWM3
// Enable global Interrupts and higher priority real-time debug events:
EINT;
ERTM;
// Main loop
for(;;)
{
// Background tasks can be added here
__asm(" NOP");
}
}
void ConfigurePwmGpio(void)
{
EALLOW;
// Configure GPIO pins for EPWM1A and EPWM1B (Phase A)
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = EPWM1B
// Configure GPIO pins for EPWM2A and EPWM2B (Phase B)
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = EPWM2B
// Configure GPIO pins for EPWM3A and EPWM3B (Phase C)
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = EPWM3B
// Configure PWM enable pin - GPIO22 (J1 Pin 3)
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // GPIO mode
GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; // Output
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; // Set LOW to enable (active low)
EDIS;
}
void InitEPwm1(void)
{
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; // Enable EPWM1 clock
EDIS;
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare values for 50% duty cycle
EPwm1Regs.CMPA.bit.CMPA = EPWM1_TIMER_TBPRD/2; // 50% duty cycle
EPwm1Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD/2; // 50% duty cycle
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on Compare A
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on Zero
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on Compare B
// Configure deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA is source for both delays
EPwm1Regs.DBRED.bit.DBRED = 50; // Rising edge delay = 50 TBCLK cycles
EPwm1Regs.DBFED.bit.DBFED = 50; // Falling edge delay = 50 TBCLK cycles
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
void InitEPwm2(void)
{
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; // Enable EPWM2 clock
EDIS;
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Set phase shift for 120 degrees (Phase B)
EPwm2Regs.TBPHS.bit.TBPHS = (EPWM2_TIMER_TBPRD * 2) / 3; // 120 degree phase shift
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare values for 50% duty cycle
EPwm2Regs.CMPA.bit.CMPA = EPWM2_TIMER_TBPRD/2; // 50% duty cycle
EPwm2Regs.CMPB.bit.CMPB = EPWM2_TIMER_TBPRD/2; // 50% duty cycle
// Set actions (same as EPWM1)
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on Compare A
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM2B on Zero
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM2B on Compare B
// Configure deadband (same as EPWM1)
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA is source for both delays
EPwm2Regs.DBRED.bit.DBRED = 50; // Rising edge delay
EPwm2Regs.DBFED.bit.DBFED = 50; // Falling edge delay
}
void InitEPwm3(void)
{
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; // Enable EPWM3 clock
EDIS;
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Set phase shift for 240 degrees (Phase C)
EPwm3Regs.TBPHS.bit.TBPHS = (EPWM3_TIMER_TBPRD * 4) / 3; // 240 degree phase shift
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare values for 50% duty cycle
EPwm3Regs.CMPA.bit.CMPA = EPWM3_TIMER_TBPRD/2; // 50% duty cycle
EPwm3Regs.CMPB.bit.CMPB = EPWM3_TIMER_TBPRD/2; // 50% duty cycle
// Set actions (same as EPWM1)
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM3A on Compare A
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM3B on Zero
EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM3B on Compare B
// Configure deadband (same as EPWM1)
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA is source for both delays
EPwm3Regs.DBRED.bit.DBRED = 50; // Rising edge delay
EPwm3Regs.DBFED.bit.DBFED = 50; // Falling edge delay
}
void ConfigureADC(void)
{
EALLOW;
// Configure ADC-A for current sensing
CpuSysRegs.PCLKCR13.bit.ADC_A = 1; // Enable ADC-A clock
// Configure ADC pins
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; // GPIO14 for IA (ADCINA2)
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; // GPIO15 for IB (ADCINA3)
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // GPIO16 for IC (ADCINA4)
GpioCtrlRegs.GPADIR.bit.GPIO14 = 0; // Input
GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; // Input
GpioCtrlRegs.GPADIR.bit.GPIO16 = 0; // Input
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 0; // SYNC to SYSCLKOUT
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0; // SYNC to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 0; // SYNC to SYSCLKOUT
EDIS;
// Initialize ADC without AdcSetMode (using manual configuration)
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // Set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; // 12-bit resolution
AdcaRegs.ADCCTL2.bit.SIGNALMODE = 0; // Single-ended mode
// Power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
// Delay for 1ms to allow ADC time to power up
DELAY_US(1000);
}
// ISR for EPWM1
interrupt void epwm1_isr(void)
{
EPwm1TimerIntCount++;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//===========================================================================
// End of file.
//===========================================================================
