OPA4192: Design Inquiry.

Part Number: OPA4192
Other Parts Discussed in Thread: OPA192

Hi Team,

I'm using the amplifier OPA4192IPWR in my board. I'm providing the output of the DAC AD3552R to the OPA4192 amplifier in my design and also used as a unity gain amplifier in another case.

The signal chain diagram is shared below

image.png

1. As it is a channel amplifier, i want only the 3 channels for my application. Can i make the unused channel as NC or any specific termination is required.

2.Is Riso resistor and Cload is mandatory in the circuit. If mandatory which values should I choose.

3.For unity gain amplifier does the below circuit is correct. Please confirm whether Riso and Cload values are okay.

image.png

Regards,

Abhishek

  • Abhishek,

    1. You should connect your unused op amp in a buffer configuration with the input grounded.  See  The Unused Op Amp—what to do? 
    2. When using an op amp to drive a capacitive load you should use an isolation resistance.  The OPA4192 data sheet has details in table 3 that help you to choose the proper value of RISO.  For a 0.1uF capacitor the table indicates that you could use between 6.2 ohms and 15.8 ohms for phase margins of 45deg to 60deg.  45deg is considered to be the minimum acceptable phase margin, so to have design margin you should choose larger that 6.2 ohms.
    3. For your circuit, the isolation resistor and capacitive load are ok.  I am not as confidant in your op amp connections. This will not work as a unity gain voltage configuration (standard non-inverting buffer).   This will also not act as a unity gain inverting amplifier (G = -1V/V).  It could work as a transimpedance amplifier, but I don't think that was your objective.

    I hope this helps, Art

  • Hi Team,

    I'm interfacing OPA4192 with DAC AD3552R. 

    I'm sharing the section wise schematics below

    First Case:

    As per block diagram shared, the output of the DACs is connected to OPA4192 with gain=2 configuration.

    As it is 3 channel amplifier the outputs from 3 channels of DAC is connected.

    1.I had provided different gain options as per AD3552R eval board configuration using a switch. Is this fine?

    2.The output current output of the DAC wants to convert into voltage output, so it wants to act as a transimpedance amplifier. Is the configuration provided is correct?

    3.Please provide the feedback on the schematics

    OPA4192 with DAC.pdf

    AD3552R eval board reference link: https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad3552r-ug-2217.pdf

    (In this instead of AD8065ARZ, i want to use OPA4192

    Second Case:

    In the second case, OPA4192 wants to configure as a buffer with Gain=1.

    1.Input to amplifier in this case will be single ended. Is my configuration correct?

    2.Please review and provide your feedback on schematics.

    OPA4192 with unity buffer.pdf

    Regards,

    Abhishek

  • Hi team,

    Please ignore the previous comment as i the file schematic file shared got mismatched.

    I'm interfacing OPA4192 with DAC AD3552R. 

    I'm sharing the section wise schematics below

    First Case:

    As per block diagram shared, the output of the DACs is connected to OPA4192 with gain=2 configuration.

    As it is 3 channel amplifier the outputs from 3 channels of DAC is connected.

    1.I had provided different gain options as per AD3552R eval board configuration using a switch. Is this fine?

    2.The output current output of the DAC wants to convert into voltage output, so it wants to act as a transimpedance amplifier. Is the configuration provided is correct?

    3.Please provide the feedback on the schematics

    6180.OPA4192 with DAC.pdf

    AD3552R eval board reference link: https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad3552r-ug-2217.pdf

    (In this instead of AD8065ARZ, i want to use OPA4192

    Second Case:

    In the second case, OPA4192 wants to configure as a buffer with Gain=1.

    1.Input to amplifier in this case will be single ended. Is my configuration correct?

    2.Please review and provide your feedback on schematics.

    8156.OPA4192 with unity buffer.pdf

    Regards,

    Abhishek

  • Abhishek,

    Response for first case:

    1. Your questions: The AD3552R eval board uses switches to configure gain, is this ok?  Yes.  This is a pretty common thing to do.  You should take into account any on-resistance of the switch as it can effect gain accuracy.  Mechanical switches have very low on resistance and generally do not impact gain accuracy.  FET switches can have high on resistance and can impact gain accuracy.  Mechanical switches wear out (they have a limited number of times they can be switched before they break).

    2. Your questions: The DAC output is a current and a transimpedance amplifier is needed to convert the current to voltage.  Is your configuration ok? Below is an image of a transimpedance amplifier.  Select RF according to your input current and desired output range.  If your input current is +/-1mA, you can choose a 10k feedback to get a +/-10V range (Vout = Iout * Rf).  Choose your Cf according to your bandwidth requirements (f = 1/(2*pi*Rf*Cf).  Do not omit CF as it helps with stability and noise.   Note that the ADI device keeps the RF resistor inside the DAC.  The ADI device has pins that allow connection of the feedback capacitor across RF.  The ADI EVM uses a rotary switch to choose the different feedback capacitors and internal feedback resistors.

    3.  Your schematic showing the OPA4192 to the DAC looks good.  The only comment is that placing a capacitor directly on the output of any op amp can cause instability (oscillations).  Small capacitances aren't necessary a problem.  Your schematic shows a 100pF capacitor and that is ok for OPA4192, but I would recommend dropping to 49pF or 10pF.  Your load may have additional capacitance which would add to the 100pF.  Strictly speaking, you can keep the 100pF but I recommend reducing that value.

    Response to second case:

    1. Your questions: Is the buffer schematic correct. Yes, your configuration is correct.

    2.  Your questions: Review the buffer schematic. Your circuit implements a buffer by installing zero ohm resistor in the feedback and do-not-populate for the resistor connected from inverting input to ground.  There is also a zero ohm resistor on the op amp output.  I like this configuration as it gives you the flexibility to change the circuit into a gain circuit if needed.  It also give you the possibility of installing a non-zero output resistor which can help if you have a stability issue.  The only other thing you could add would be DNP feedback capacitors.   I don't think this is needed, but could be added in case you want to have flexibility with this circuit in the future.

    I hope this helps.

    Best regards, Art

  • Hi  

    Thanks for the feedbacks.

    In first case.

    2.The Cf capacitor where should i place in my schematics. As you mentioned in a image whether i should connect the Cf capacitor in between NCAP0 pin and PCAP0 pin of the DAC.

    3.I had connected Riso 360E series resistor at the output as a recommendation for 100pF output capacitor. As per your feedback, adding 10pF in place of 100pF should i keep the same 360E at the output or should i change the resistor value. Also, in my current design the 100pF capacitor is provided as an option, it is not populated. Is it mandatory to provide that capacitor at the output.

    Kindly confirm the above queries.

    Regards,

    Abhishek

  • Hi  

    What will be the supply current of V+ and V- pins.

    Regards,

    Abhishek

  • Abhishek,

    1. The CF capacitor is in parallel with RF.  CF and RF are generic terms for feedback component.  These components connected from the op amp output to the inverting input.  In your case RF is inside the ADI DAC, and the CF is external (connected on the NICAP and PCAP pins).
    2. The isolation resistor should help with capacitive load.  With your isolation resistor you can use either 10pF or 100pF.
    3. The supply current is relatively independent of the supply voltage.  See graph below from OPA192:

    Best regards, Art

  • Hi  

    1.In the current board design, the output of the AD3552R DAC is first processed by an OPA4192 configured as a transimpedance amplifier. The signal then passes through an isolation transformer, followed by a unity-gain filter stage using another OPA4192. Finally, the signal is buffered using an LT1227CS8#PBF.

    Could you please confirm whether cascading these two buffer/amplifier stages could introduce any signal integrity issues or signal loss in the system?

    2.In the second case, a single output from the OPA192 amplifier is distributed to 14 channels of OPAx192 series buffer amplifiers.

    Could you please confirm whether feeding one signal into 14 buffer amplifier channels could introduce any loading, signal integrity, or stability issues?

    Regards,

    Abhishek

  • Abhishek,

    1. Cascading two buffers will have minimal impact on signal integrity.  Each amplifier will have some noise and distortion, so the total noise and distortion will be slightly worse.
    2. Connecting an OPA192 to the input of 14 OPA192 buffers should not be a problem.  Each OPA192 has about 1pF of input capacitance.  The traces will also add input capacitance.  Assuming the total trace capacitance is 10pF, the capacitive load will be 14pF + 10pF.  The OPA192 can drive over 200pF so you should not have any stability problems.  The input impedance of OPA192 is very high so that will not load the amp either.  As a precaution you could add a 10 ohm resistor between the driving amp and the 14 buffers.

    Best regards, Art