THS4551: Gain Verification

Hi Nishant,

The FB+ and FB- pins are the outputs of the amplifier, brought to the other side of the package to allow for easy routing for feedback without having to go all the way around. This means the feedback resistors on pin 2 goes to pin 1 and pin 3 goes to pin 4. Your schematic will need to be altered then, the 3.3ohm resistors are currently in parallel with the 1.2kohm feedback. 

I'm assuming the 3.3ohm is meant to be isolation within the feedback. 

If your input signal is 2.8V peak, is that 2.8Vpp (+/-1.4V) or 0V --> 2.8V? That will help determine if your gain is correct to limit the output to 1.8Vpp for the ADC. If it is 2.8V peak I think the output will saturate you might have to attenuate it. 

For simulation, I would have one to double check DC input/output common-mode voltage ranges and transient response for output ranges, can also be used to check frequency response. You can use this file attached for example:

THS4551 Transient Eval.TSC

However I would also check stability with this file attached. Here you can check loop gain and phase margin with whatever capacitive load or filter you might be expecting to drive the ADC. I would keep the split supplies here the model seems to react funny when you do a single-supply.

THS4551 Stability Eval.TSC

Hope this helps.

Thanks,

Evan

1. I would like to use this example circuit as a reference to troubleshoot my hardware. In my design, the THS4551 is connected to an ADC, and the VOCM pin is driven with the ADC VCM output (0.9 V).
2. With no input signal connected, I observe noise/oscillation at the outputs. Additionally, both VOUT+ and VOUT− measure approximately 1.8 V. I am unable to understand why the outputs are at this level when no input is applied. Could this indicate an issue with the common-mode loop, feedback network, ADC loading, or circuit stability?
3. The example shows an input signal of ±18 V while the THS4551 is powered from a 5 V supply. Could you please explain how the circuit processes this input and what the expected output waveform and voltage levels are? When attempting to simulate the Page 33 example circuit, I am encountering SPICE convergence issues and am unable to obtain a stable operating point. Are there any recommended simulation settings, initial conditions, or analysis procedures that should be used with the THS4551 macro model?
4. Canyou please provide the simulation analysis for that circuit.

Could you please advise:

• How to analyze the Page 33 circuit step-by-step?
• What output voltages should be expected with no input applied?
• Whether this reference circuit can help identify the cause of the oscillation and 1.8 V output level noise observed in my hardware?

Thank you for your guidance.

Hi Nishant,

For your hardware, is it the same schematic as your first post? I wouldn't think it is an issue with the common-mode loop, but more an issue with the feedback/stability or ADC loading. What load is it driving? If you play with any of those parameters does the situation change?

Figure 9-6 works because it is in a attenuator configuration. G = Rf/Rg = 1k/4.99k = 0.2V/V. The paragraph just below the figure does a good job describing the considerations. 

To summarize it though: 

Voltage Biasing:

• Output common-mode voltage (VOCM) = 4.096 V / 2 = 2.048 V
• Source signal common-mode (VCM) = 0 V
• Nominal input pin voltage (VICM), this is a resistor divider from Vocm to the input pins with the Rf/Rg = 2.048 V × 4.99 kΩ / (4.99 kΩ + 1 kΩ) = 1.71 V

• A ±18 V input applied with G=0.2V/V gain produces a 7.2-VPP differential output
• This corresponds to 3.6Vpp on each output or ±1.8 V swing on each output side around the 2.048 V common-mode
• The resulting output range is 0.248 V to 3.84 V (relative to ground), well within the 0.2 V headroom margins of the 0–5 V supply rails

• The output swing feeds back an attenuated input common-mode swing: ±1.8 V × (4.99 kΩ / 5.99 kΩ) = ±1.5 V around the 1.71 V bias
• Input common-mode range: 0.2 V to 3.2 V, safely within the available -0.1 V to 3.8 V input range 

• The source must sink 0.34 mA (2.048 V / 5.99 kΩ) of common-mode level-shifting current to bring the 0 V input VCM up to the 1.71 V operating point
• The source must also drive an apparent input load of 5.44 kΩ (per Equation 4 in the datasheet)

You can see the attached TINA file to play with these considerations. 

THS4551 Figure 9-6.TSC

Thanks,

Evan

I used THS4551 in my hardware to drive an ADC. After assembling the board, the supply current increases to around 700 mA immediately after power-up, even when no input signal is applied. What is the reason of that adc is taking differential input of max capability of taking differential Voltage (+-2Vpp)

Schematic of hardware same as stated in first post 

If your current is going up to 700mA, that sounds like some kind of short on your hardware coming from somewhere. An oscillation wouldn't cause that. What is the supply value of the THS4551 if you measure it on the pin? If you disconnect various parts of the circuit does it recover?

In this case, the input voltage applied to the amplifier is greater than the supply voltage rail, and from the application note/schematic it appears that this condition is acceptable. Could you please explain the operating concept behind this? I would like to understand whether I am missing something regarding the input common-mode range, internal protection, or the FDA architecture.

Also, in the reference schematic, a 1 kΩ resistor is connected across the differential outputs. Is this resistor mandatory in every differential-output application, or is it only required for specific operating conditions such as output biasing, stability, ADC interfacing, or load matching?

In my schematic, this 1 kΩ differential load resistor is not present. Could you please clarify the purpose of this resistor and whether omitting it could affect circuit operation or performance?

Thank you for your support.

Hi Nishant,

Have you been able to simulate the circuit for the specific input range you are using in your design. In your previous post you mentioned that Iq in high even with no input? Can you share what you mean by this? Is the input OP1 grounded when you see this 700mA value? 

Regarding the 1kohm load, this was just the load condition that was set when highlighting the device in the datasheet. Omitting this and having an open load I believe would not be causing the issue you see. The THS4551 is affected by load conditions which is why simulating the circuit would be highly recommended however a 1kohm load is not mandatory.

Best Regards,

Ignacio

1.My schematic shared at the start the single-ended input is connected to the non-inverting input of the THS4551. However, most datasheet examples apply the single-ended signal to the inverting input. Is my configuration correct? What difference should I expect in the differential outputs between these two configurations?

2. My output differential signal appears to remain entirely positive. I expected one output to increase while the other decreases around the common-mode voltage. Could you explain the expected differential output behavior when using a single-ended supply and a VOCM of 0.9 V?

3. The THS4551 datasheet shows several capacitors in the feedback network and at the outputs. In my simulations, adding or removing these capacitors does not noticeably change the transient output. What is the purpose of these capacitors, and under what conditions do they become important?

4. My design conditions are:

• • Supply: 5.4 V single supply

  • Input signal: 0 V to 2.8 V (random signal)

  • ADC differential full-scale input: 2 Vpp

  • ADC VREF: 1 V

  • VOCM: 0.9 V (allowed range 0.5 V to 1.3 V)

  • Can TINA-TI generate a random input signal for this type of simulation? If not, what input waveform is recommended??

5. For verifying the THS4551 before connecting it to the ADC, is transient simulation sufficient, or should I also perform stability analysis (loop gain/phase margin)? Which simulations are considered essential when driving a high-speed pipeline ADC?

6.The ADC outputs LVDS data, and my FPGA supports LVDS inputs directly. Is any external LVDS driver or buffer required, or can the ADC LVDS outputs be connected directly to the FPGA with proper routing and termination?

7. Does TI offer a 14-bit pipeline ADC with a TINA-TI simulation model so that I can simulate the complete signal chain with the THS4551?

8.I have already fabricated my PCB, but I did not include an LVDS connector. What is the recommended method to bring the LVDS outputs out for testing? Would an SMA pair be appropriate, or is there a better approach?

9.Since most high-speed ADCs provide only IBIS models and not SPICE models, what simulations and laboratory tests should a design engineer perform to validate the ADC interface for the correct output that is coming from opam or not?

Please tell the values of Rg and RF for calculation of gain. Is there calculator you have please tell and share with which input to give what single ended signal and what values should be and 3.3 ohm that in rgt package in schematic i put. My design requirement of 0 to 2.8V random signal and coming differential output in -1V to 1V .

Is RGT package is good to select or any other Best package for noise as well thermal performance as RGT package is having FB- & FB+ of ths4551 from which if I doesn't connect anything that is fine or 3.3 ohm smd resistor i put as done in schematic. 

And please tell after differential output i need to put anti aliasing filter before giving to high speed ADC can you please tell how to design that part and please tell it should be calculated how values should be calculated. Or balun and all that circuitry should be there. 

If my adc is quad abd I am using 8 ths4551 and one Vcm pin of adc connects to all 8 VOCM of FDA then I need to care of what?? I should put 0.1uF cap at all 8 VOCM pin or only one 0.1uF is enough to the adc only.

 If my FDA signal. If my output signal is all +ve and all -ve then  it is a differential output or not ?? As according to me it is single ended output if I am wrong please tell differential output . Also explain the role of common mode Voltage it is constant or varying signal coming from ADC?? And please tell in simulation what can be done. Please tell how we can simulate . 

And also explain the role of AC coupled and DC coupled signal and there simulation and please tell what suits my requirement how to identify or need to run both. 

Please provide all information as well simulation and all for that. So that easily done analysis this 

Check this simulation 

• FDA: THS4551.
• ADC internal reference: 1 V.
• ADC input: Differential.
• AVDD = 1.8 V (generated from an LDO).
• ADC VCM = AVDD/2 = 0.9 V, connected directly to the THS4551 VOCM pin.
• THS4551 supply: Single supply, 5.4 V.

Input Signal

My input signal is single-ended:

• Minimum = 0.2 V
• Maximum = 2.8 V

I want the THS4551 to convert this into the proper differential signal required by the AD9257.

Simulation Issue

I am simulating the circuit in TINA-TI.

When I apply a sine wave or square wave with:

• Amplitude = 1.4 V
• DC Offset = 1.4 V

(the resulting signal swings from approximately 0 V to 2.8 V),

I observe that:

• The differential output is correct only up to around 0–1.8 V input.
• Above this range, either OUT+ or OUT− starts clipping.
• One output peaks while the other no longer swings symmetrically.
• The differential output becomes distorted and is no longer correct.

This appears to be output clipping.

• Is the clipping caused by incorrect gain, incorrect common-mode voltage, or output swing limitations of the THS4551?
• For a single-ended input, is it recommended to drive:
  • IN+
  • or IN−?
    Does one configuration provide better performance?
• My ADC full-scale differential input is approximately 1.8 Vpp. What closed-loop gain should I use in the THS4551 for a 0.2 V to 2.8 V single-ended input?
• What resistor values are recommended for the THS4551 in this application?
• Is an output RC network required between the THS4551 and the ADC? If yes, what values are recommended for:
  • Series resistors
  • Differential capacitor
  • Any common-mode capacitors
• Should I place a 1 kΩ resistor between OUT+ and OUT−, or should I only use the recommended RC filter?
• If an anti-aliasing filter is recommended, would a Butterworth filter be the preferred choice? If so, what filter order and cutoff frequency would you recommend for a 30 MSPS sampling rate?
• How should I perform stability analysis for the THS4551 in TINA-TI?
  • Should I perform loop-gain analysis?
  • What phase margin should I target?
  • How should I choose the compensation capacitors, if required?
• Is a 5.4 V single supply the optimum supply for the THS4551 in this application, or would another supply voltage provide better performance?

Any recommendations on the complete analog front-end—from the THS4551 output to the ADC input—including gain, filtering, stability, and recommended passive component values would be greatly appreciated.
Add 3.3ohm in schematic simulation 

THS455_New_Schematic.TSC

I need output like -1 to 1V 2Vpp signal possible or not please tell me 

Hi Nishant,

There are a lot of questions here but I'll try to answer what I see as the major themes to start off.

On the Simulation:

• Your input signal is basically unipolar, only going +0V to +2.8V and back. So the outputs differentially only swing in one direction as well.
• The THS4551 outputs can only swing about 200mV above Vs- (0V or ground in this case). The TINA Model captures this behavior.
• Since Vocm is at 0.9V, and the outputs can only swing to 0.2V, each output can only swing about 700mV negative.
• In the case for In- = 2.8V and In+ = 0V, the output has to swing 2V differential. 
  • One output swings +1V and the other swings -1V from 0.9V common-mode
  • However the one that swings negative can only swing 0.7V negative. This leads to the massive asymmetry and weird results you are seeing in simulation.
• The fix would be to add a voltage pedestal to the un-driven leg at 1.4V. This means the differential input will be +/-1.4V. 
• This allows the outputs to swing in both directions as well, bringing differential output back to 2Vpp.
  
  
  

On the ADC:

• TI does have 14-bit pipeline ADCs. However you are better off posting a separate question asking about how to properly simulate your ADC and how to drive the LVDS pins to make sure our High-Speed ADC team sees the question, I don't have the appropriate knowledge. You can also ask about appropriate alternatives to the AD9257, a quick search shows the ADS5281 and 5282 but they will know more about their catalog.

On the ADC Filtering:

• An Anti-aliasing filter is recommended. Probably some amount below your nyquist depending on what kind of signals you are measuring. For 30MSPS your nyquist is 15MHz so something slightly below that. 
• A lot of the THS4551 datasheet configurations show an active Multiple Feedback Filter (MFB) configuration. You can see this application note for information on that: https://www.ti.com/lit/ab/sdaa099a/sdaa099a.pdf though typically that filtering scheme is for slower ADCs and bandwidths in the kHz range. 
• You can either drive some passive RC filter, in which case you should make sure you can drive the appropriate cap load with the right isolation resistance.
• Or you can use the circuit you have an tweak the values a little bit.
  • Your 1.4kohm will form an RC filter with your input capacitance. 
  • You can tweak that input capacitance to get the filter bandwidth you want.
  • This will create a pole in your feedback that will effect stability. You can tweak your feedback capacitance to create a zero that will cancel that pole. 
• Here I estimated some values that gave me 10MHz bandwidth.
  • 10MHz with 1.4kohm Rg --> ~11pF input capacitors. 22pF differential.
  • 10MHz with 1kohm Rg --> ~16pF feedback capacitors. Usually I have the zero before the pole though to make sure its ok with variations. 
  • This gave me a bandwidth of ~11MHz. Quick stability sim showed 60+ degrees phase margin. I would aim for at least 45 degrees.
    

Other General Thoughts:

• Definitely simulate stability for your filtering scheme. I believe I gave you example simulation files earlier.
• 1kohm differential load is not required but it can help simulate the open-loop gain of the model slightly more accurately.
• I think RGT is the best package for the inclusion of the FB pins plus thermally it is quite better than the other packages. However your FB pins are wired incorrectly in your first post (the FB pins ARE the output pins just routed to the other side of the package).
• Having your input signal on In- or In+ mostly doesn't matter. The FDA will always invert your input (180 phase shift) so having the single-ended input on In- keeps it in phase with the input.

Hope this helps you get started.

Thanks,

Evan

THS4551_1_Schematic.TSC

I am using the THS4551 as a fully differential driver for the Pipeline ADC and would appreciate your guidance on a few observations from my simulation.

System Details:

• ADC Supply:

  • AVDD = 1.8 V

  • DRVDD = 1.8 V

• ADC Input Range: 2 Vpp Differential

• It is recommended that give input differential input to ADC not single ended input

• ADC Common-Mode Voltage (VCM): 0.9 V (provided by the ADC)

• ADC Internal Reference: 1 V

• THS4551 Supply: 5.4 V

• Input Signal: Single-ended square wave

• Gain Configuration: 0.6 V/V

Questions:

1. With the gain configured to 0.6 V/V, I expect approximately 2 Vpp differential output, but the simulation shows only about 1.68 Vpp differential. Could you help identify the possible reason for this discrepancy?

2. The waveform at one of the outputs (VF4) appears distorted even though the input is an ideal square wave. What could be causing this distortion? Is it due to slew rate, bandwidth, output loading, feedback network, or another factor?

3. From a stability perspective, does the simulated response appear acceptable, or are there signs of instability that should be addressed?

4. Since the ADC operates from a 1.8 V supply while the THS4551 is powered from 5.4 V:

   • Is it acceptable to operate the amplifier and ADC from different supply voltages?

   • Are there any reliability or interface concerns with this configuration?

5. What is the minimum recommended supply voltage for the THS4551 while still achieving:

   • 2 Vpp differential output,

   • VCM = 0.9 V,

   • good linearity,

   • and stable operation?

6. Can the THS4551 be powered directly from 1.8 V while driving the ADC with a 2 Vpp differential input? If not, what supply voltage would be recommend as the optimum choice considering performance, output swing, and design margin, stability?

7.  Also tell is there any protection circuit recommended such that if Output of Amplifier goes above 2Vpp output clamps or there should be some safety margin for not blowing ADC. Please tell to get optimum SNR and Linearity in input what should I do as ADC should not have problem in driven. AVDD is 1.8V for ADC Absolute max rating of AVDD, DRVDD is -0.3V to 2V . 
8. Tell AIN+ &AIN- of ADC what it should be as input voltage range is 2Vpp differential input voltage mentioned 

Thanks.

Hi Nishant,

1. With your 2.8V input differential X 0.6V/V gain = 1.68Vpp output. You'll need to increase your gain to ~0.714V/V to get the output to 2Vpp. There are a couple other things to note though:
   1. Your DC pedestal on In- is +2V, while your other input swings between 0V-->2.8V. 
   2. On positive swings there is a 0.8V input differential. With the 0.6V/V gain the output swings 0.48V differentially.
   3. On negative swings there is a -2V differential. With the 0.6V/V gain the output swings 1.2V differentially.
   4. This combines for the 1.68Vpp differential. 
   5. To make this symmetrical around 0.9V, the DC pedestal on In- should be 1.4V, or the mid point of how much your SE input swings.
2. VF4 appears distorted because of the differences between how the In- and In+ legs are being driven. In+ is being driven by the source, while In- has to play catchup so-to-speak with the virtual short inputs. This is just an inherit property of driving an FDA SE to Differential. 
3. Stability wise it is a bit on the border with as an attenuator. With 0.6V/V signal gain its noise gain is 1.6V/V or ~4.08dB. There is a small resonance in the device's open-loop gain that degrades the phase margin here, I simulated that you have about 35 degrees. 
   
   
   Attenuators can be tricky for FDAs as they often rely on the fact that a signal gain of 1V/V for them is really a noise gain of 2V/V which helps for stability. Having some extra feedback capacitors to bring the noise gain back up at higher frequencies when it crosses the AOL will bring the phase margin back up. See this attached file.
   6354.THS4551 Stability Eval.TSC
4. It is acceptable to drive the FDA and ADC from separate supplies. For pipeline ADCs there isn't really a way around that, FDA supply ranges are more limited. There are interface concerns when doing this to not damage the ADC inputs. 
5. Minimum supply rating for the THS4551 is 2.7V. This will still work for your case of 0.9V common-mode and 2Vpp differential outputs. 
6. The THS4551 can't be powered with 1.8V, it is 2.7V minimum.
7. Some clamping diodes would be what I would think on the output of the FDA to help clamp the outputs to not be beyond the max input range of the ADC. Sort of like external ESD diodes. This will add some capacitance to the output which will degrade linearity and stability a bit so some isolation resistance would be recommended. Or the LMH6553 is another option that has integrated clamps and is common for driving these ADCs. However its supply and output ranges are more limited, you'll need split supplies in that case most likely. 
8. I'm not understanding this question. 

Thanks,

Evan

Supply: Single supply, VS+ = 5.4V, VS- = GND

=== SIGNAL SOURCE CHARACTERISTICS ===
- Input pulses: random amplitude, min 0.2V to max 2.8V (2.6Vpp)
- Rising edge slew rate: 80V/us
- Falling edge slew rate: 45V/us
- Input noise: 80uV
- Source can drive a max capacitive load of 25pF
- Signal frequency 7.5-10MHz, sampled by ADC at 30MHz

=== DESIGN GOAL ===
Differential output of ~2Vpp (1.94-1.95Vpp acceptable) at OUT+/OUT-,
matching ADC full-scale input.

=== CURRENT SCHEMATIC (attached) ===
- Rf1 = Rf2 = 1.5k
- Rg1 = Rg2 = 2k → signal gain = Rf/Rg = 0.75, noise gain = 1.75
- C2/C3 = 16pF across Rf1/Rf2
- C4 = 22pF differential across IN+/IN-
- VOCM driven externally, currently measuring ~0.9V at that pin
- IN+ driven by single-ended source through Rg1
- IN- biased through Rg2 to a fixed pedestal voltage
- R3-R6 currently 0 ohm (placeholder, direct routing to SMA test
connectors for bench measurement)
- FB-/FB+ pins on the RGT package currently unused/floating

=== QUESTIONS ===

1. GAIN CHECK: With 2.6Vpp input (0.2V-2.8V) and gain 0.75, expected
differential output is 1.95Vpp. Can someone confirm this gain
setting (Rf=1.5k, Rg=2k) and cap values (16pF feedback, 22pF
differential input) are the right combination to hit ~1.94-1.95Vpp
output with good linearity, or is there a better resistor/capacitor
combination recommended for low thermal noise and stability at
this specific gain?

2. TINA-TI SIMULATION - PWL SLEW RATE INPUT: I'm trying to build a
PWL input source with rising edge slew rate 80V/us and falling
edge 45V/us between 0.2V and 2.8V. My transient simulation is set
to run for 10ms (matching my PWL input duration up to 10ms), but
the simulation does not converge when I introduce the fast edges -
[describe exact error you're seeing here, e.g. "time step too
small" or specific error text]. What transient simulation settings
(max time step, tolerances) are recommended when simulating
sub-microsecond edges within a multi-millisecond transient run?
Simulation file (with example pulse input) attached.

3. LOAD CAPACITANCE / MINIMIZING CHAIN CAPACITANCE: My source can
drive a max capacitive load of 25pF. How should I size C4 (input
differential cap) and any input RC to minimize total capacitance
in the signal chain for fastest settling, while still meeting my
80V/us rising edge requirement? Is 22pF too high for this edge
rate given my Rg=2k?

4. INPUT TERMINATION / 49.9 OHM SHUNT: I've seen reference designs
that place a 49.9 ohm shunt resistor to ground before Rg when
driving a single-ended input from a coaxial source. Is this
required in my case (detector output driven through coax to the
THS4551 input), and if so where exactly should it be placed
relative to Rg? I noticed a difference in measured signal with vs.
without the SMA connector/coaxial cable in my bench setup - could
this termination resolve that?

5. OUTPUT LOAD RESISTANCE: Datasheet/design notes for my downstream
ADC recommend a load resistor >=100k ohm in the path from the FDA
output to the ADC input. How should this be implemented - in
series, in shunt, or as part of the anti-alias filter network
between OUT+/OUT- and the ADC?

6. STABILITY ANALYSIS:, Cf = 16pF, and
Cdiff = 22pF,
What is the recommended approach to achieve maximum stability
while keeping capacitance from increasing further at high
frequency (i.e., avoiding additional peaking from parasitic or
compensation caps)?

7. BANDWIDTH REQUIREMENT: Given my signal bandwidth of interest is
7.5-10MHz and the ADC samples at 30MHz, what closed-loop bandwidth
should I target for this stage, and does my current Rf/Cf (1.5k,
16pF) combination support that bandwidth without excessive peaking
or rolloff?

8. VOCM PIN: What is the input impedance of the VOCM pin on the
THS4551? I am currently measuring ~0.9V at VOCM with 0.1uF and
0.22pF [confirm which caps you actually have here] on that node -
is this an acceptable operating point for VS+ = 5.4V single
supply, and are these decoupling cap values reasonable, or is a
different value recommended for this application?

9. PROBING / TEST POINTS: For bench debugging, is it acceptable to
probe directly at IN+ and IN-, or are there signal integrity
concerns with placing a probe there (loading effects on the
feedback network)? Given the output is differential routing, what
is the recommended test point method - solder-in test hooks, or
direct SMA connectors at OUT+/OUT- - to avoid signal integrity
issues from probe wire length/loading when measuring on an
oscilloscope?

10. FB-/FB+ PINS: The RGT package has FB- and FB+ pins currently
unused in my schematic. Should these be connected for my
application, or is leaving them unterminated acceptable?

11. GENERAL SCHEMATIC REVIEW:   currently 0 ohm placeholders
routing directly to SMA test connectors, to be populated with
real values once initial bench results confirm correct FDA output
before connecting to the ADC. Please review the attached schematic
for any other issues before I proceed to board bring-up.

I'm comparing stability across a few schematic variants (different Rf/Rg, C4, and input termination values) and have the following questions on simulation setup: 1. For loop-gain/phase margin analysis, do I need to include both feedback legs (Rf1/Rg1 and Rf2/Rg2, including the non-driven IN- pedestal network) and the VOCM decoupling network in the sim, or can the loop-gain probe be placed with only the driven side present?

2. Should the output-side network (R3-R6, currently 0 ohm, ADC-facing side) remain fixed while I sweep input-side values, or does the loop-gain measurement require the actual final output loading to be present for an accurate result?

3. What is the recommended method in TINA-TI to break the loop for AC loop-gain analysis on the THS4551 (built-in stability probe vs. manual break with large L/C injection)?

4. For gain margin, is TINA-TI's AC Transfer Characteristic sufficient to extract both phase margin (at 0dB crossover) and gain margin (at -180 deg phase), or is a separate analysis mode needed?

5. For THD, what input amplitude/frequency is recommended to characterize distortion representative of my ~1.95Vpp differential output swing, and does TINA-TI's FFT tool report THD directly from a transient run, or does it need manual harmonic extraction?

6. For noise analysis, should I run TINA-TI's noise analysis with the full schematic (including Rf1/Rg1, Rf2/Rg2, C2/C3, C4) to get output-referred noise across my 7.5-10MHz signal band up to the 30MHz ADC sample rate, and is there a way to get integrated RMS noise directly rather than spectral density only?

7. My differential feedback caps (C2/C3 = 16pF) and differential input cap (C4 = 22pF) are included in the attached sim - is this the correct placement for stability analysis, or should input capacitance be modeled differently (e.g., split single-ended caps at each input pin instead of one differential cap) for an accurate loop-gain result?

attached  TINA-TI simulation file (.TSC) with
example pulse input.

THS4551_Running_Random_Pulses_Eval.TSCTHS4551_New_Random_Eval.TSC

png2pdf.pdf

• Can you please reply above question and tell the equation to calculate input impedance of ThS4551 in any gain configuration to drive Vcm pin if impedance is large to drive then how to reduce tell the method for that also Vocm pin directly coming from ADC 

And probing at input pins of THS4551 is recommended or not ?? IN+ &IN-

Hello,

I would like to kindly follow up on this thread. Could someone please help review my question when time permits? I would appreciate any guidance or suggestions regarding this issue.

If any additional information, measurements , I will be happy to provide them

Thank you for your time and support.

Hi Nishant,

Apologies for the delay, I was out of office for a week.

On the general design considerations:

• Thanks for the extra information on your input signals. I forgot that we were looking at square waves earlier. A 10MHz square wave worst case would need more bandwidth than the 10MHz filter scheme I proposed earlier as an example. You'll have to tweak what I do as needed.
• 80V/us on a 2.8V step --> 35ns rise time --> 0.35/35ns ~=10MHz at least required, however since it is a 10MHz square wave you'll want the harmonics to make a periodic edge clean.
• 16pF + 22pF only has ~9MHz of bandwidth. After playing around with values, I found that only having 2pF in the feedback and 1pF in-between the inputs gave the cleanest response in the time domain, no gain peaking with 60 degrees phase margin.
  
  
  
  
  THS4551_newlynew_schematic.TSC
  THS4551 newlynew Stability Eval.TSC
• It's worth noting that a 30MSPS ADC may not see a 10MHz square wave very cleanly. You'll may want to consider 10X the fundamental frequency for bandwidth so 100MSPS at least in this case. If you end up going that way, you may want to consider the THS4541 as an ADC driver instead which is luckily pin-to-pin compatible with the THS4551 in RGT package. 

On the board implementation and debug:

• Probing IN+ and IN- pins directly is possible. However most probes introduce like ~10pF of capacitance which is going to change your results and stability conditions just from probing. It's ok to quickly double check things but just know your signals at that time will not look as good. 
• The 49.9ohm termination resistor could help you in your case since your signals are so fast, and it seems like you are using the coax cables and/or bringing different PCBs together. I would recommend a place holder before the Rg resistors to ground like R6/R7 below. With a 50ohm source you'll need to add a resistor the equivalent of the termination in parallel with 50ohms so ~25ohms. 
  
• With your 0ohm placeholders on the outputs, and the implementation of the FB pins, I think the schematic looks good other than the termination resistors on the Rg resistors.

On the TINA questions:

• I'm not able to replicate your issues with converging on your TINA files. They run fine for me and the results look ok. 
  • It's worth noting on your piecewise linear inputs, your rise times are 10us >> 35ns needed for 80V/us.
• THD isn't modeled in TINA unfortunately. 
• For noise, you can get the total integrated noise at each frequency by checking the Total Noise checkbox when running a noise analysis. 
  
• Gain margin can be looked at the same time as phase margin. 
• The THS4551 model was made before we started accurately adding Zo so the output loading doesn't affect the model much.
• A manual break is better for stability analysis.
   

Hope this helps.

Thanks,

Evan

I am currently evaluating the THS4551 and, during initial testing, I am driving the VOCM pin directly from an external linear power supply to verify the amplifier operation before connecting it to the ADC's VOCM output.

On my PCB, I have provided a 0 Ω resistor between the ADC VOCM node and the THS4551 VOCM pin. After successful testing, I plan to populate this resistor so that the ADC drives the VOCM pin directly.

For the initial testing phase, what is the recommended method to connect the external VOCM source?

• Should I provide an SMA connector on the PCB and apply the external VOCM voltage through a coaxial cable?
• Or is it sufficient to use short wires/test clips from the external linear power supply to the VOCM test point?

Since VOCM is a DC common-mode reference and not a high-speed signal, I would appreciate TI's recommendation on the best PCB test approach to minimize noise and obtain reliable measurements.

Hi Nishant,

For the Vocm pin, short wires/test clips are sufficient to drive the Vocm pin. Given how it is a DC common-mode reference like you said.

SMA connectors as seen on many of our EVMs are meant more for us to evaluate the dynamic performance of the Vocm pin such as bandwidth, slew rate, etc. Practically speaking though its rare to need to drive the Vocm pin through a coax.

Thanks,

Evan

Hello TI team,

As the FDA gain configuration changes, I understand that the effective input impedance seen by the signal source also changes.

Could you please help me with the following questions?

1. How can I calculate the input impedance seen by the signal source for a given FDA gain configuration?
2. Which parameters and equations should be used to determine the input impedance?
3. If I am driving the FDA from a 50 Ω function generator during laboratory testing, how should I choose the input termination resistor?
4. Should the FDA input always be terminated with 50 Ω, or should the termination resistor be selected based on the calculated input impedance of the FDA?
5. What is the recommended input termination method for accurately evaluating the FDA and ADC performance in the laboratory?
6. After laboratory testing, the FDA input will be driven directly by my actual signal source instead of the function generator. In that case, is input termination still required, or does it depend on the output impedance of the signal source?
7. If the actual signal source not function generator is not connected and the FDA inputs could be left floating, what is the recommended way to terminate or bias the FDA inputs to avoid floating inputs and ensure proper operation? So that termination resistor according to gain what it should be and  how it will be calculated without affecting gain of the system.

Can I measure my settling time in hardware from FDA?  And in simulation?

Hi Nishant,

For bench testing, driving with 50ohm sources and coax cables is common as the cable and trace lengths between bench equipment can be pretty long. A good rule is if 1/4*wavelength of your max signal frequency is greater than your trace and cable length then you need to think about controlled impedance and termination resistors. It is recommended for evaluation to make sure your input signals are clean. 

If your actual signal source in your application is close enough or without cables, i.e. on the same PCB and nearby, then you don't need to worry about impedance matching/input termination.  

For the termination resistor and input impedance:

• Your input impedance is your termination resistor (Rt) in parallel with Rg, or Rt || Rg = 50ohms
  • If your Rg is big enough this usually means Rt is close to 50ohms.
• Make sure to match the impedance of the undriven leg with the driven leg including the signal source impedance. 
  • Rt on the undriven leg = Rt(driven) || Rsource, if your Rg is large then its usually near 25ohms. I often like to just mimic the driven leg and 50ohms to ground to make it easy.

The actual math can get very complicated if you let it. But I have this calculator you can use to determine a good termination resistor. 

FDA_Resistor_Calculator.xlsx

To keep inputs from not floating some pull-down resistors to ground for the input termination will help. As low as you can get away with I would think, I've seen up to 1kohm but that can introduce noise, depends what is driving it normally and if that is still connected.

Settling time is a tricky thing to measure in hardware. Simulation is better, but what type of settling are you concerned with?

Thanks,

Evan

Hello Evan,

I calculated that the required attenuation is approximately 0.71 to convert a (0.2 V-2.8V) single-ended pseudo-analog signal into a 2 Vpp differential signal for a DC-coupled pipeline ADC. I selected Rf1 = Rf2 = 1 kΩ and Rg1 = 1.4 kΩ, Rg2 = 1.43 kΩ with a 51.1 Ω input termination resistor. For stability, would using 2 pF capacitors across the feedback resistors and 1 pF capacitors on the inputs be a good starting point? Also, before connecting the ADC, is it acceptable to evaluate the differential amplifier using an SMD-to-DIP adapter board with through-hole resistors and capacitors, and is a 1 kΩ load at the amplifier output suitable for initial hardware testing? Finally, since I do not yet know the ADC sampling capacitance or sample-and-hold resistance, what would you recommend as a good starting point for the RC filter between the differential amplifier and the pipeline ADC?

My ADC sampling rate is 15 MSPS, the maximum input signal frequency is 7.5 MHz, and the input signal consists of pulses with varying amplitudes occurring at different time intervals (pseudo-analog signal). Any recommendations for the ADC interface and test setup would be appreciated.

Hello TI Team,
I am using the THS4551 with a 5 V single supply and a single-ended pseudo-analog input varying from approximately 0.2 V to 2.8 V, which needs to be attenuated and converted to a 2 Vpp differential signal for the ADC.
I want to provide a variable DC offset provision with my Single ended input signal that can be adjusted during testing. However, I do not want this externally added DC offset to appear at the ADC input. The same offset that is added to the signal should be subtracted/cancelled before the differential ADC input, so that the ADC sees only the desired signal component.
What is the recommended way to implement this add-and-subtract offset function with the THS4551? What provision should I include in the differential signal path/ADC interface to ensure the externally selected offset is cancelled accurately?
I would also like to keep the feedback resistor and feedback capacitor fixed. Please advise whether this is possible and what stability checks are required after adding the attenuation and offset network, particularly for noise gain, bandwidth, phase margin, and feedback capacitor interaction.
Please suggest the recommended circuit approach.
Thanks.

Hi Nishant,

If a DC offset is added to your SE input signal, then adding that same offset to your undriven leg would be the best way to remove it I would think. The amplifier should differentially subtract that DC offset with its differential gain.

For example here if you have 1.4V DC offset on Vin then adding that 1.4V to the undriven leg will subtract it out:

There could be a few ways to implement this depending on what your signal source is.

How much offset do you need to calibrate out?

Thanks,

Evan 

I have an adjustable DC offset-calibration range of 0 to 2.2/2.3 V, although the expected normal offset is approximately 1.2 to 1.7 V. Best resistor combination values for lower thermal noise and integrated noise.  ADC input voltage is 2Vpp so make how to make near to around 1.8Vpp or 1.9Vpp margin for noise and ADC max input value. So in Hardware what to be put so that anytime it can be adjusted on the bench no external supply needs to be connected 

As stated, Signal is pulses means pseudo analog signal input single ended 

I see, thanks for explaining the offset ranges. Seems pretty large, I'll have to think about this I'll get back to you about a scheme. It might have to be filtered out before interfacing to the FDA instead.

Thanks,

Evan

Hi Nishant,

To generate that DC offset I think this scheme would work: https://www.ti.com/lit/an/sbaa343a/sbaa343a.pdf 

It could run on the same 5/5.4V supply you have, it uses a DAC and precision amp to create that DC offset. 

V-OFFSET in this diagram should be applied to the other input of the FDA as I drew in the above post.

It uses DAC80504 and offers OPA227 or OPA188 as devices. I think each of those look good.

Thanks,

Evan