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LOG114 photodiode protection

Jamaal_Charles
Genius 3245 points
Other Parts Discussed in Thread: LOG114, LOG114EVM

Hi TI,

We are planning to use the LOG114 for optical measurement, and have followed the LOG114EVM design very closely.   However, we'd like to understand the design a little better.  The EVM has guarding around the photodiode inputs.   I understand why it is necessary to guard the bias voltage pin, but it looks like the diode is also partially guarded by the Vref.  Why is that done? 

We'd like to understand the best practice(s) for guarding with low level current signals with this part?

Thanks,

Jamaal

  • 0
    TI__Genius 14317 points

    For the circuit shown in Fig. 5 in the EVM User's Guide, the inputs for A1 and A2 are at Vbias and the output voltages of A1 and A2 are dependent upon the input currents to each and the resulting voltage drop of the diodes in the FB path. Since A1 and A2 inputs are at Vbias, it makes sense to me to use Vbias guard traces around each input to prevent leakage currents from adding to the input Iphoto and Iref currents. I suppose that partial guarding by Vref could be secondary protection against leakage currents that could couple from Vcc to the high impedance node at Rll and Iref input to A2.

  • 0 in reply to Jeffery Pfarr
    Genius 3245 points

    Hi Jeff,

    So, I guess I don't understand why the reference current signal passes in between the pads for the photodiode rather than taking a shorter route over the top and then allowing the vbias trace to loop further around the photodiode pads for further guarding.  It also doesn't look like Vref is getting much opportunity to guard the high impedance side of the reference current signal going into pin 3. 

    This is what I would have though made more sense. Or does this ruin the guarding of the reference current?

  • 0 in reply to Jamaal_Charles
    TI__Genius 14317 points

    Jamaal,

    I would have built a Vbias guard ring around the Iphoto and Iref inputs. That way, leakage currents from outside the ring would not get to the LOG114 inputs and leakage currents from the LOG114 input pins would be minimal since the guard trace and LOG114 inputs are at the same potential.

    After looking at the EVM some more....The photodiode is connected between Vbias and the LOG114 I1 (Iphoto) input so it looks like the designer may have routed the Iref trace closer to the Vbias guard trace so that the guard trace guards both I1 and Iref inputs at least from one side. Perhaps the unique leakage paths of this particular board demanded this less intuitive guard trace design approach. Or, since the photodiode can be connected to the EVM board in three different configurations per the EVM User's Guide, maybe this design was a best compromise for all three input configurations.

    See 3-41 in the attached document for more on guard trace design.

    guard_ring.pdf