Design Support: OPA549 parallel configuration amplifier oscillation

Peter,

You have two OPA549 set to 5.12A maximum output current (Rcl=7.15k) while the other three are set to 5.25A (Rcl=6.8k); thus, I am not sure if you refer to the total ~7A sinking current or is this output current per op amp?  If latter is the case, you have an obvious problem.  Also, do you use a heat sink to dissipate the power in OPA549 op amps?  Without the heat sink, the thermal junction-to-ambient resistance is 30deg C/W which could result in the op amps heating up to 160deg C resulting in intermittent thermal shutdown.  As the junction temperature changes between 160deg C (off) and 140deg C (on), OPA549 goes in and out of thermal shutdown, which could be misconstrued as OPA549 oscillation.  

Depending where you connect the load and what the output voltage is, the power dissipation inside the op amp may be different which could explain why the instability is seen while OPA549 is sinking current but is not there while it is sourcing output current.

Hi Marek,

The 7A draw is shared by all OPA549 devices (I confirmed that they are sharing the current reasonably well --within a few mA of each other). All devices share a large (350W) heat sink, and when the tab is probed with a thermal couple, none of the devices should have been going in to current limit mode, though I am aware current limiting is slightly asymmetric.

For the time being, I am focusing on making sure my power supply is as clean as possible, but I suppose my real question is: is there anything intrinsic about the 549s that prevent them being used in a configuration like this one?

I have deep experience in power op amp circuits.  There are several questions I will ask below to help work you towards a robust power op amp solution. The architecture you are using is known as Master-Slave.  U5 is the Master and U1, U2, U3, U4 are the Slaves since they follow whatever the Master output voltage is. 

1) You want to set the Slave (U1-U4) current limit  20% higher than the Master current limit so that if there is a short condition on the output the amplifiers will share power dissipation equally.  This will occur since the master will lower its output voltage first and the slaves will follow.  In addition the output of the Master amplifier should never drive closer to the rail than the input common mode voltage of the slaves. 

2) We need to get a range of Load Impedances to analyze this circuit for stability. For capacitive loads in power op amp circuits one can usually create a stable circuit for no more than one to two decades of cap load change without switching in different compensation.  What is the load? Piezo? Motor? Programmable Power Supply?

3) What is the purpose of changing C5 in your circuit?  Are there varying closed loop frequency responses you are looking for?

4) What are frequencies and amplitudes of input voltage? Step? Square wave? DC? Sinewave?

5) What size of Bolt are you using to mount the power op amp tabs to the heatsink?

6) What torque is being used on the mounting bolt?

7) Are you using a shoulder washer on the mounting bolt?

8) What voltage potential is the heatsink tied to?

9) What insulator is between the op amp power tab and heatsink?

Also please send me data sheet or MFR/Part number for the 0.1ohm power resistors.

Hi Tim,

Thank you for looking in to this with me.

1) I will change the design accordingly. That is a good hint.

2) That is difficult to determine. The load impedance is something the customer will attach to the system. In general, it will be a highly capacitive load with a small series resistance. This is part of a battery test system. It is highly unlikely to be an inductive or switched current source.

3) C5 is just a schematic representation of a bank of switched capacitors. In our industry, it is common design practice to provide some capacitors to adjust the bandwidth for the amplifier. The capacitors are not there for stability purposes (the amplifier should be stable with any combination of the capacitors), but to assist in the measurement.

4) There are two set point voltages (in practice, this is a summing amp), there is a very low frequency <~10Hz dc operating point voltage (-3 to +3 v), and a high frequency (1kHz-10kHz) small amplitude (~10% of the set voltage) sine source.

5) We are using a #6x32 machine screw to mount the opamp tab to the heat sink

6) We do not have a torque specification on the screw. It is 'beefy-arm' screwdriver tight though

7) We are using a small lock washer with the screw.

8) The heatsink is floating and electrically isolated from the rest of the case.

9) No insulator is used on the heatsink mounting tab, the heatsink is isolated.

10) the power resistor is an Ohmite 43FR10E (datasheet can be found here (from octopart): )

Just as a side note, I realized that in simulation, the amplifier intersected the 0db point at -40db/dec. I added a 10K 5% in series with each of the switched caps to ensure that the crossing is about -20db/dec. Also, I added some filter caps to the power lines, which helped too. But, again, i am interested in any other 'gotchas' this configuration may throw at me. I would still appreciate any notes you might have to offer.

Thanks again, Tim.

-Pete

I will be spending time tomorrow on a detailed analysis of your circuit.  Relative to 2) above give me your best engineering guess as to the load model.  Any min/max guess on capacitance? Any model of the battery as a load?  To ensure robust operation we should look at the load impedance and ensure we can keep this loop stable.  Relative to 9) above I would assume you use thermal grease or check out THERMSTRATE.  For best thermal conductivity you need to fill the air gap between the tab and the heatsink with thermally conductive material.  I will comment back on the other points after my detailed analysis. 

Not sure if attached will be of any help relative to load modeling. 

In parallel with my analysis I recommend you study the 4 parts on Op Amp Stability in the link below as the techniques described there-in will be used to analyze your power op amp circuit. 

http://e2e.ti.com/support/amplifiers/precision_amplifiers/w/design_notes/2645.solving-op-amp-stability-issues.aspx

Relative to all mechanical mounting considerations I attach recommendations for OPA549.  Note per 6) above you might want to consider calibration of your "beefy-arm".

Final Power Tab mounting consideration - see attached.

Is the LTC6240 for U6 and U7 what you really have in the design? If so its max supply voltage is 7V total and you are running it at 16V!  Also is AD8065 what is in the real design for U8? Need to make sure analysis is based on final design as it is rather detailed.  I will gladly share the details once it is completed.

I made some assumptions on the load (see attached).  I also assumed all small signal op amps were AD8065 so I could do some preliminary looking at the overall design.  In your original post you mention an oscillation at 7A sink current.  Did you ever record the frequency and amplitude of this oscillation with resistive load and what resistive load was used?  Frequency of oscillation often can help us diagnose stability issues. Based on other information you have supplied C6 is always 100pF and in parallel with C6 can be C5 = 1nF or 10nF or 100nF or 1000nF implying a minimum of C5=1nF? Also what detailed arrangement of "switches" are you using to change values of capacitor C5?  Also are you using cables (length and type) to connect your circuit to power supplies?  What cables (length and type) are used to connect the output od the power op amp to the Load?

For a robust real world product I would recommend the current limit bypass capacitor as shown in figure 2 of the OPA549 datasheet. In addition since I suspect you will use cables to connect the load I recommend the snubbers shown on figure 8 in the OPA549 datasheet. Also recommend a power schottky from output to +8V and Output to -8V to protect from any real world transients.  In addition put transient voltage suppressors on each supply to ground.  I attach a document to help explain this.

Edited to get include responses to all posts.

Regarding 2) For the moment, we are working on getting a model. Our Electrochemical scientist says there hasn't been a lot published on the type of battery this will study, but for the time being, a capacitance of 0.1F-0.5F is reasonable for an order of magnitude guess. He will (hopefully) be able to get back to me soon on a model which we can try out.

Regarding 9) we are using a silicone thermal grease on the tab.

Regarding the stability slides: I am reading those and I may have a few questions.

Regarding screw torque) My arm is NIST Tracable ;-). We will add the torque to our manufacturing specifications. Thank you for the tip, I didn't see a torque called out in the datasheets, or app notes. I must have missed it.

Regarding the LTC6240) Yes, we are using the HV variant of the chip. On the 'real' schematic, they are tied to +/- 5V. the AD8065 is the real amplifier being used. To be honest, I did not expect this much help. I will produce a more accurate subassembly schematic. May I directly email/fileshare it to you?

Regarding your Jun 26 19:36PM Post) I did record the frequency (324KHz), though the oscillation was not purely sinusoidal. I will have to modify the device, but I will reproduce the oscillation and post a diagram of it in a follow up post. Regarding the capacitors: C6 is always present in the feedback loop. C5 is actually a group of 4 discrete caps connected to a ADG412BR analog switch and can be switched in to the feedback loop in any combination. So, C5 represents any combination of 1nF,10nF,100nF,1000nF caps. I instructed spice to just switch them all in  to get an idea of what would happen. The supplies are wired to the device using a double run of 14awg/41 stranded to connect the screw terminals on the circuit board to the supplies. We don't have lengths worked out yet, but for the prototype, the lengths are about 18inches. You can see a picture of the setup here: http://imgur.com/ZbsVupn.

Regarding your Jun 26 20:12PM Post) We will add the caps over the current limit resistors. In the real design, diodes are present to try to clamp back emf. I will read over your EOS document though, and change the design accordingly.

With respect to sending you a more complete schematic, is LTspice a dirty word around TI or can I send it in LTSpice format?

At TI we are a diversified company and are open to all forms of SPICE. I would like to speed up our investigation and as I believe you are in the US we can also use telephone calls.  If you are okay post your email address and I will send you an email with my contact information.   

Dear Tim and Peter,

I have designed a very similar circuit to drive a magnetic field producing solenoid (.4 Ohms, 100 mH) and I observed oscillations of a comparable frequency to those you described when each op-amp sinks about 5A of current. The circuit is stable when sourcing current. The only difference is that my master is in a non-inverting configuration, hence I see oscillations when the set point is negative. Also, I directly sample the load voltage for feedback without the buffer staged. I tried to add a snubber in parallel with the load, but it did not seem to affect the oscillations. Any advice would be greatly appreciated. Many thanks.

-William Bowden

Hello Peter,

Thank you for your feedback. I am happy to hear you got your circuit working (there is hope for me yet). In response to you comments.

1) My load is also inductive, about 500uH, but I was under the impression that inductive loads should not hurt stability as compared to capacitive loads.

2) My master op-amp is in non-inverting configuration which limits my ability to role of the gain given the static gain of one. A bit of an oversight on my part.

3) What was the main layout features that helped to ensure ensure stability.

After playing around with the circuit I am pretty sure I know what the problem is. I completely removed the output resistors on the master such that it sources no current and acts as a voltage buffer for the slaves. I still see oscillations at the output which tells me the slaves are not unity gain stable when the output is close to the voltage rail while driving the load. I guess when they source significant current and the output is close to supply voltage the open loop properties of the op-amp changes making them unstable. I tried various snubber circuits with no luck. I could change the unity gain followers to non-inverting amplifiers to reduce the feedback factor and hopefully push them into a stable region, but that would requiring hacking up my pcb. Thank you for you help. 

William