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Hi all,
I am developing Class-D Power AMP(35W, 6.78MHz) for wireless charge.
The plan to make a circuit is as below picture.
Triangle wave is made by TLV3501+OPA357 and then it make pulse which will drive FET gate and have a dead time by using comparator.The specification of Op-Amp for 6.78MHz should be more than 40~60V/us for slew rate and 130MHz for Bandwidth.
I would like to know that this process is right for signal to Gate driver.
Could you give me some advice for this plan? please recommend proper device if some device is wrong.
Thank you for your help.
Marek,
Thank you for your answer and simulation file.
I have more questions.
To drive FET gate, I am going to use two pulses.
one is made of inverting hysteresis comparator for high side and the other is made of non inverting hystresis comparator for low side.
The dead time is needed to avoid that high side and low side turn on simultaneosly.
I would like to know whether this concept is right or not.
Please give me some advise.
Thank you.