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Hi Folks,
in the following, I will refer to the and the Figure 35 and Figure 36.
Most of the time when I use solid plane on the 2 layer PCB, I connect them to power supply GND. Similar to the Figure 36, where GND is used as IC's REF input and as I understand, the cooper plane under the chip is also connected to it.
But somewhere I heard that instead of GND I should connect the plane to Vg potential (Figure 35), that is common mode potential of the input.
So I would like to know is it true or not? How can I choose the right net for the plane filling? Any advise would be welcomed.
Regards,
Toth, Norbert
Ni Norbert,
yes, this makes sense.
With a ground plane under the input signals unequal stray capacitances to the ground plane can convert common mode noise into differential noise by forming an imbalanced voltage divider. When using a common mode signal plane under the input signals, on the other hand, the unequal stray capacitances are also referencded to the common mode signal and no imbalanced voltage dividing can occur.
Having said this, consider that the common mode signal VG is generated actively by the help of RG/2 resistors and 1/2OPA2131. Or, by other words, VG cannot unlimitedly absorb EMI by itself. So, I would additionally shield the common mode shield (cable shield and common mode signal plane) by a signal ground shield (0V). But make sure, that the stray capacitance between the common mode shield and the signal ground shield is minimal. Otherwise the 1/2OPA2131 might see a too high capacitive load at its output and might become unstable.
See also this interesting appnote discussing guarding methods:
Kai
