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Hi team,
Could you please clarify the absolute maximum rating for each input pin of LM7171?
It is necessary to design the input protection for LM7171.
Furthermore, if you could suggest the recommendable schematic to protect LM7171 input from EOS damage with respect to gain flatness in Av=+2 as high frequency as possible, it should be appreciated!
Best regards,
Iwata Etsuji
Hello Iwata,
While we don't have that spec on the datasheet, the limit is usually Vs+ + 0.7 to VS- - 0.7. The LM7171 also has a maximum differential voltage of +/- 10V. What voltages are you expecting to see inputted to the device?
Best,
Hasan Babiker
Hi Hasan-san,
How about the attached solution to protect the input of LM7171?
Best regards,
Iwata Etsuji
Hello Iwata-san,
Your proposal is very detailed and promising. I do notice you are setting up your clamp voltages with zeners using quite a lot of power and then showing higher impedance when asked to clamp. That pushes the output into cliopping which is not well modelled. Perhaps you should just use a couple of step down regulators operating at lower quiescent (but with lots of decoupling on the other side of your clamping diodes) to keep the output from limiting when overdriven - might as well help recovery time going to this much trouble.
Hello Michael-san,
Thank you for your reviewing and comments.
At first, as you pointed out, I had put the LDO instead of zeners on the input clamp circuit.
However, I replaced with zeners since I was just afraid some linear regulator has poor sink capability and it might cause problem on much higher voltage than clamping voltage such as surge noise...
Of course, this is just my assumption, so if you have any more appropriate circuit example of the input protection circuit(is it with LDOs?), please share it with us.
Best regards,
Iwata Etsuji