Hello,
Last month my colleague Ernest Montllo posted a question regarding how to achieve the best signal-to-noise ratio in high gain (G=50) differential amplifiers for 16-bit ADC. With good criteria, it was suggested to change to TSH4541, with lower noise a higher bandwidth.
Now we are designing a new application with lower settling time requirements and want to use TSH4551 again.
- Input signal maximum differential amplitude of ±66 mV.
- Common mode < ±100 mV
- Gain must be around 50 to have a full differential output range of ±3.3V that goes directly to a 16 bit ADC.
- Step response to 95% must be between 600 ns to 800 ns.
We have tuned the circuit to achieve RMS noise below 200µV and a settling time t< 600 ns. However, we have some doubts:THS4551_600ns_CurrentSenseSim.TSC
1. Is there risk of unstability with the current circuit? On the past we have faced stability problems when using small output resistors on TSH4551 with high gain.
2. We do not have a clear idea of the contribution of filtering capacitors around FDA to noise analysis. A fast noise analysis based on TSH4551 Section 9.1.1 and [1], gives us a noise of 300 uVrms; on the contrary, simulation gives a 190 uVrms value. Is there any Application Note with further information about this topic?
Thank you very much for your help!
