LMH7322: window comparator

Hi Joe,

Thanks for your email. I want to use them with indendent output. Could you please share the simulation with 200 MHz input signal.

Thanks

Hi Srikanth,

I just need to know the following information about your design before I simulate:

1. Channel A and Channel B voltage supply values

2. Window voltage thresholds (for example: Vh = 7V and Vl = 2V)

3. Voltage of the input signal

4. Input signal type (sine, square.. etc)

5. Any additional information that is specific to your design

After receiving this information, I will try to get the simulation results to you by close of business Tuesday (9/22).

Thanks,

Joe

Hi Joe,

Please find the below info. i am looking for LVDS output from both the channels.

1. Vcci = 5 V, Vcco = 2.5 V

2. Vh = 2.55 V, Vl = 2.45 V and

3. Vinpk-pk = 200 mv with 2.5 V off set -

4. trainagular with 200 MHz frequency.

The input signal is sensed volatge signal from power supply of 48 V switching at 25 MHz frequency. I am expecting my outputs as shown below. Please let me know if you need more info.

Thanks

Joe is still reviewing things and will get back to you by tomorrow.

Chuck

Hi Joe,

May I know if there is any update on this?

Thanks

 Hi Srikanth,

As depicted by the schematic, I used Channel A on the device in a non-inverting input configuration for your lower threshold (VL). I used channel B in an inverting input configuration for the high voltage threshold (VH=2.55V). The table below depicts the input/output behavior I implemented.

The outputs are correctly in the LVDS output range (1.0V to 1.4V) and I have implemented minor hysteresis (20mV) using R5 and R6 corresponding to the plot I included from the datasheet.

You can omit R5 and R6 to have no hysteresis. Please reach out if you think the simulation needs tweaking and/or if you would like me to change the design parameters.

Thanks,

Joe

Hi Joe,

Thank you for the results and these are very helpful. May I know the name of simlation tool that was used for this design and can I get the simulation files to try for our design.

Also, the input signal is a 25 V sqaure wave and we are trying to use a 10:1 (10 k : 1k) potential divder network to sense the voltage and apply to the comaparator input. May I know if this has any effect on the LMH7322 input side?

Thanks in advance.

YSK

Hi YSK,

I will inquire about ways that you can simulate the circuit and get back to you by end of business day tomorrow (9/23). As long as the voltage seen by the input pins is within the operating voltage range of Vee-0.2V to Vcci-0.5V, then the divider circuit should have little to no impact. By the end of tomorrow, I will confirm if the voltage divider does not impact the circuit. I will also try to find out a way to get you simulating!

Thanks,

Joe

Hi Joe,

Thank you so much. Will be looking forward for the update about the volatge divider.

Thanks

YSK

Hi YSK,

As long as the voltage divider network keeps the voltage within the operating range for the LMH7322, the comparator will have no impact. The only concern I would have is filtering your input signal when using a resistor (with inherent parasitics) network. I would make sure your signal out of the divider is as expected.

I have attached the PSpice for TI file that we used below. I believe the simulation is PSpice compatible. Click on the hyperlink if you need to download PSpice for TI. If you encounter any issues with the simulation or have any further questions, let me know.

Thanks,

Joe

LMH7322_window.zip

Hi Joe,

Thank you so much for the simulation tools and file. May I know if I can connect the LE and VEE pins to GND.

Also, in order to filter out the input signal noise, I am thinking of using a small filter capacitor (pF) in parallel with the 0402 sense resistor. 0402 will have little parasitics. But adding a filer cap is going to effect my primary ciruit performance due to the rectangular pulse nature. Could you please suggest if I can go ahead with sense resitor (0402) n/w alone. Any suggestions on this are apprciated.

Thanks

Srikanth

Hi Srikanth,

On page 15 of the datasheet, it states that the LE-not pin should be connected to Vcco pin via a 10 kΩ resistor and the LE pin should be connected to Vee via a 10 kΩ resistor. So to answer your question, you can connect Vee to ground but you should place a 10 kΩ resistor between Vee and the LE pin if you are not using the latch functionality.

As far as filtering your input signal, I would just make sure you are aware of the corner frequency of the low-pass filter that your resistive network (with parasitics) would create. Your input signal would turn into a rounded pulse and lose its high frequency components. Are you trying to sense your input only with passive components?

Thanks,

Joe

Hi Joe,

Thanks for the clarification about the GND connection.

At the moment, we are thinking of passive components as we can't afford much delay. But we are also looking at highspeed active sensing techniques. If there any op-amps available we are ready to use them in our design. Could you suggest any high bandwith active sensing methods using TI opamps.

Thanks

YSK

Hi YSK,

Let me ask some of the other engineers in the comparators group and I will get back to you by the end of the business day tomorrow. 

Thanks,

Joe

Hi Joe,

Will be loking forward.

Thanks

Hi Srikanth,

I am going to forward this thread to the High Speed Amplifiers group to see if they can find a product for your application. Using an active, high speed component to attenuate the input signal will hopefully mitigate filtering of the input (when compared to a resistive network). I hope you get a solution soon.

Thanks,

Joe

Hi Joe,

Thank you for the update. Looking forward to hear from them.

May I know if there is any refernce PCB design and layout guidelines availble for LMH7322. Especially to route the  the LVDS ouput pins.

Thanks

YSK

Hi YSK,

I think this User's Guide should help answer your question.

Thanks,

Joe

Hello YSK,

Just want to confirm I've correctly understood the previous conversation before looking into an amplifier:

• You need to attenuate 200MHz 25V square wave. What is the rise time of your input? What is the offset of this signal?
• The noise from your voltage divider is too large and so you added capacitance in the pF range to help filter.

• I'm guessing you can't reduce voltage divider resistances further due to power consumption?

• If my understanding for the above are correct, then we can use an amplifier in a unity-gain configuration to isolate the resistance of your voltage divider and create your low-pass filter at the output of the amplifier before going into the comparator.
• Please help provide any amplifier requirements/preferences to help narrow down your search. What supplies are available here? Do you have power consumption, noise, cost, dc precision requirements? Please let me know of any other requirements you may have.

Best,

Hasan Babiker

Hi Hasan,

I would like to attenute the following set up. Please see the below figure. The two square wave voltage signals (25 MHz) would be sensed at the two terminals of a Flying capacitor. We want to attenuate the difference of these two signals ( =  the voltage across the 4 uF flying cpacitor is 25 V) by a factor of 5. I am thinking of using 2k : 8k potential divider network to achive this. Your suggestions on this will be appreciated

1. Rise time is 0.3 - 1 ns. the offsets are shown in figure.

2. I  want to add a pF capcitors to filter the noise in case of resitive divider network. But would like to know high bandwidth (30 MHz) active sensing options.

3. We would like to have as much less power consumtion as possible for this sensing circuitry.

4. Also the delay introduced by the active sensing circuit should be less than 30 ns if possible.

We would like to have a band width of atleast 30 MHz for the active sensing. I guess a diferential amplifier is good candidate but, if you can provide suitable suggestions that would be great. 12 V, 5 V and 3.3 V power supplies are availble. The sensed output signal should be noise free of high frequency components (> 30 MHz) and with the least possible voltage ripple (< 10 mV). At this point we are not worried about the cost.

Please let me know if any more information is required.

Thanks

Srikanth

Hi Hasan,

I would like to attenute the following set up. Please see the below figure. The two square wave voltage signals (25 MHz) would be sensed at the two terminals of a Flying capacitor. We want to attenuate the difference of these two signals ( =  the voltage across the 4 uF flying cpacitor is 25 V) by a factor of 5. I am thinking of using 2k : 8k potential divider network to achive this. Your suggestions on this will be appreciated

1. Rise time is 0.3 - 1 ns. the offsets are shown in figure.

2. I  want to add a pF capcitors to filter the noise in case of resitive divider network. But would like to know high bandwidth (30 MHz) active sensing options.

3. We would like to have as much less power consumtion as possible for this sensing circuitry.

4. Also the delay introduced by the active sensing circuit should be less than 30 ns if possible.

We would like to have a band width of atleast 30 MHz for the active sensing. I guess a diferential amplifier is good candidate but, if you can provide suitable suggestions that would be great. 12 V, 5 V and 3.3 V power supplies are availble. The sensed output signal should be noise free of high frequency components (> 30 MHz) and with the least possible voltage ripple (< 10 mV). At this point we are not worried about the cost.

Please let me know if any more information is required.

Thanks

Srikanth

Hello Srikanth,

Your picture wasn't properly added, please use the "insert media" function to add this to your post.

Best,

Hasan Babiker

Hi Hasan,

I am sorry for that. Please see below

Hello Srikanth,

Rather than bandwidth, the main limitation here seems to the potential slew rate that you will require. Even at 1ns, the rate of your input will be 25,000 V/us which is beyond the capability of even current-feedback amps. So what is the maximum rise/fall time that you are willing to introduce to your 5V output? or is the only requirement here that the delay must be under 30ns?

Best,

Hasan Babiker

Hello Hasan,

That's correct. We aren't much bothered about the input square waves rise/fall times, because our focus is on the differnece between the two signals which is going to be a constant 25 V with certain amount of ripple (100 -500 mV). Also, the ripple frequency is 25 MHz. As long as we are able to capture the 25 MHz ripple, we are good. Yes, we want to have a delay of < 30 ns.

Thanks

Srikanth

Hello Srikanth,

The attached diff amp configuration should be able to meet your requirements. The THS4631 is the only FET-input amplifier that can achieve the slew rate requirements that you require. Please let me know if you have any questions. 

YSK_Ripple_Input.TSC

YSK_Differential_input.TSC

Best,

Hasan Babiker

Hi Hasan,

Thank you so much for your suggestion. I am planning to use  1 pF in parallel with the two 1.65 K resistors to filter out the noise and for stability. May I have your comments about its' effect on bandwidth of the design. Does it have any consequences on sensing of 25 MHz ripple voltage. Please advice.

Thanks

Srikanth

Hello Srikanth,

I agree this would be helpful both from a noise & stability perspective. Your - 3db bandwidth looks to be 34.7MHz now so you can reduce the cutoff frequency of the low-pass filter at the output as needed.

Best,

Hasan Babiker