• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 2916 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OPA1642: Low-Noise OPA1642 Pre-amp

Jonathan Keller
Prodigy 20 points
Part Number: OPA1642

Hi,

I'm working on a product that requires signal conditioning of an audio signal from a wide variety of sources to under 3 V peak (for the input of an ADC). Technically the full-scale input should be about 1.15 V peak but in order to avoid damaging the ADC it must be kept under 3 V peak. Noise should be kept to the minimum possible.

To accomplish this, I designed this schematic using the OPA1642 audio op amps. The input stage is set up as a unity buffer with a bootstrap for high input resistance. The second stage is set up to provide gain anywhere from 1/10*Vin to 333*Vin. Finally the output is clamped to about +/- 2.5 V to protect the ADC.

The idea is that the user will be able to adjust the gain to maximize the ADC's resolution.

I'm looking for general feedback on the design of the circuit as I've never attempted something like this. It seems to work well in simulations. One problem I've noticed is that the second stage contributes a lot to the noise output in simulations when the pot (R6) is turned up (output~250 nV/root-Hz). Oddly enough, R4 is shown to contribute the most to the noise output in the simulation, where I would have expected R6 to be the noisiest at high values. I'm not sure how to get the range of gain I need with less noise though.

Any help, pointers, criticisms are much appreciated!

  • 0
    TI__Genius 12325 points

    Jonathan,

    From a noise perspective, R4 is effectively in parallel with R5 + R6, therefore the noise contribution will never exceed that of a 2.98k resistor (~7nV/rtHz). Is there a particular reason why your second stage is inverting? Right now if you want to reduce the noise contribution of R4, you will have to reduce its value, and if the value is reduced too low it will begin to cause excess distortion is the first stage amplifier.

    I'd recommend changing the second stage amplifier to non-inverting, and re-calculating the gain network using a significantly lower values. You should also consider that since a non-inverting amplifier will provide high input impedance, there is essentially no need for the bootstrapped input buffer as well, and both stages could be replaced with a single-stage. 

  • 0 in reply to John Caldwell
    TI__Genius 12325 points
    I just re-read your post and saw the requirement to attenuate as well as amplify, which explains the need for an inverting stage after the buffer.
    I guess if you don't want to change the overall circuit topology, you can drop the value of R4 to reduce the noise.
  • 0 in reply to John Caldwell
    Prodigy 20 points
    John Caldwell,

    Thank you for getting back to me so quickly! Yes, we need -20 dB of attenuation in case the input signal is of higher amplitude than the ADC can take. If I reduce R4, I also have to reduce R5 in order to maintain the -20 dB of attenuation which gets tricky considering the op amps are rated for ~30 mA output at room temperature. I could still reduce it a little bit.

    If the most noise is coming from the 2.98k resistor then I think I'm okay. For some reason the simulation was showing noise in the range of microvolts with the pot (R6) turned all the way up. I have no idea where it came up with that.

    Thank you!