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AM335X: RMII direct connection between two devices

Jaroslaw Karwik
Prodigy 205 points
Other Parts Discussed in Thread: AM3352, DP83848C

Hi,

I am designing dual Sitara system ( 2x AM3352) and I want to connect them using RMII directly (MAC to MAC) - without using PHY.

According to these threads:

- http://e2e.ti.com/support/arm/sitara_arm/f/791/p/262120/1283080.aspx#1283080

- http://e2e.ti.com/support/arm/sitara_arm/f/791/t/212517.aspx

it is not supported, but I do not agree ( I have been using RMII connections for FPGA based devices) as there were no details about possible issues.

So - lets go over some possible problems (lets assume 100Mbit full duplex connection):

1) Timing issues for clock/data lines.

In RMII mode we use external 50MHz reference, so the clock is symmetric for both devices.  So there should be no issues with timing/skew - in case of  real MAC/PHY connection  Rx/Tx data must be synchronised to the external reference clock, so the once data is valid on Tx lines it  has same timing (related to reference clock ) on Rx lines. And I have not seen anything which suggests that Tx and Rx timing on RMII is different

2) Preamble and start bit synchronisation

Well, we have full sync using TX_EN line connected to CRS_DV. In our case CRS_DV is rather RX_DV as there is no data loss ( see DP83848C - http://www.ti.com/lit/an/snla076a/snla076a.pdf ). We also will not have any data shifts ( 2-bit packets will be transfered 1:1 )

So - is there anything I am missing ? I can route these signals through FPGA to emulate PHY, but this would raise a bit board cost and at this point I would not even know where the catch is.

Best regards,

Jarek

PS. References to similiar questions:

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/172049.aspx?pi301021=2

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/50706/180798.aspx#180798

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/t/31757.aspx

  • 0
    TI__Guru**** 393215 points

    No, this is not possible. The AM335X supports only MAC to PHY connection. MAC to MAC is not supported.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 205 points

    Well, my point it that such connection  ( MAC to MAC  in RMII full duplex mode with external clock) cannot be distinguished from MAC to PHY connection. 

    I would kindly ask you to tell me what I got wrong in my assumption - I have implemented several FPGA designs using RMII and PHY devices and in all the cases these connections were fully symmetrical and could be used without PHY's.

    Is there anything specific about Sitara MAC implementation ? I just cannot gues what could go wrong reasding RMII specification.

  • 0 in reply to Jaroslaw Karwik
    TI__Guru**** 393215 points

    I will ask the factory team if they can elaborate on this, but they are on a very busy schedule right now and response may be delayed.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 205 points

    Basically you would not need factory people, but design architect specialized in ethernet. Or somebody specialized in ethernet switches ( which implement MAC to MAC interfaces)

    My assumption ( about MAC to MAC in RMII mode) comes from reading RMII specification and I would say should be true for all devices compliant with RMII specs.

    I agree that full MAC to MAC connection is not always possible. But I think that in this specific mode ( RMII, external clock, full duplex) we have a special case which should work. 

    Well, there are some reservations (RMII rev 1.2) 

    5.8 Loopback
    During normal operation TXD[1:0] and TX_EN shall not be loop ed back to RXD[1:0]
    and CRS_DV, respectively. Loopback for diagnostics is unspecified in this document.
    Note that loopback across this interface is impossible since the collision detection is
    done in the MAC, which assumes independent receive and transmit control signals.

    But this limitation is not valid in full duplex mode, which by definition does not have collisions and both RX/TX path are completely independent.

    Anyway - thanks for help, and pressing it forward.

     

  • 0 in reply to Jaroslaw Karwik
    TI__Guru**** 393215 points

    Hi Jaroslaw,

    After discussing this scenario with the factory team we have concluded the following: 

    1. The MAC to MAC use case was not considered by the design team nor ever tested by silicon validation or application teams.  

    2. There may be use cases where this works, but is not a use case we support. In other words, if you go this path and have issues you would be on your own.  

    3. There is at least one known case of a customer connecting the AM335x MAC (RMII) directly to the MAC of another processor and found it worked reliably. 

  • 0 in reply to Biser Gatchev-XID
    Prodigy 205 points

    Thanks a lot for clarification,

    I was afraid there is something missing, but once this is just untested case I am more confident I can try it on my design.

  • 0
    Prodigy 200 points
    just curious. is that set (connect them using RMII directly (MAC to MAC) - without using PHY with AM335x) working ?
    thanks!
  • 0 in reply to Rogerio Almeida
    Prodigy 200 points
    I have similar set up in my hardware (connect micre switch with am335x using RMII) So , it is ok to give me more detail information. you need to modify cpsw.c to support the switch, or let the switch to act as PHY.

    thanks!
  • 0 in reply to Yolanda Zhong
    Prodigy 205 points

    I ended up in processors to far away o route RMII, so I have  combination of ordinary phy's and switches.

    So I was not able to verify the idea ( I still think it would work).

  • 0 in reply to Jaroslaw Karwik
    Prodigy 200 points

    you mean that you combine of oriinary phy/s and switches in cpsw.c code ?

  • 0 in reply to Yolanda Zhong
    Prodigy 205 points

    Basically yes - I have modified the code a bit so I can force either auto negotiation with phy or fixed connection with external RMII switch port. it is simple, you need just to force 100Mbit full duplex connection on switch port.

    I have two processors - one uses ethernet ports independently ( phy + switch), the other is configured for switch ( but also connected to phy and switch).