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PCM1864: LRCK duty selection in Master mode

Mochi
Genius 3885 points
Part Number: PCM1864

Hello,

Can we get DSP mode LRCK (Frame sync) output in Master mode?

 

At Table 37. Page 0: Register 11 Field Descriptions

Bit4 shows

0: duty cycle of LRCK is 50% (default)

1: duty cycle of LRCK is 1/256 (similar DSP mode)

But we cannot have 1/256 Frame sync output.

 

The other hand, at Figure 46. Audio Format for TDM

There is comment as below.

50% Duty Cycle (Master Mode)

1BCK or 50% Duty Cycle (Slave Mode)

 

It is just confirmation, which is correct?

 

Regards,

Mochizuki

  • 0
    TI__Mastermind 23050 points

    Hey Mochizuki-san,

    Both of the statements are correct. PCM186x can operate with a 1/256*fs pulse when in slave mode, but in master mode it will always output a 50% duty cycle FSYNC. It is not possible to have 1 BCK FSYNC output in master mode. Since most TDM interfaces use the rising edge of FSYNC to start the frame, it shouldn't really matter if you use a 50% duty cycle FSYNC unless you are trying to align data to the falling edge of FSYNC, in which case you could just invert the FSYNC. I would think though that the processor you are using probably has the capability to change the format as needed though.

    Best,

    Zak 

  • 0 in reply to Zak Kaye
    Genius 3885 points

    Hi Zak,

    Thank you for youe confirmation.

    Regards,

    Mochizuki