Hi Team,
Could you tell me which clock Do output timing is based on, LRCK or BCK?
BCK clock has some jitter in my customer system and sometimes it goes down before LRCK down edge. They chose left-justified mode so they would like to confirm how dealing with the first bit data if BCK goes down before LRCK down edge.
Regards,
Takashi Onawa
I do not have an answer to that query with certainty. However I can give my interpretation . It will have to be checked practically with the Chip.
Please refer to the diagram:
The device gives out 16 bit Left justified data. But it allows 32,48,64 BCK/LRCK. As can be seen from the 48BCK/LRCK case in the diagram the DOUT had zero data from BCK no 17 to 24.
The Case with jitter would have 17 BCKS within the High time of the LRCK. The Chip would consider this to be 48BCK/LRCK case and the BCK with jitter would be BCK no 17 and DOUT would be zero. The next BCK would be D15 for Right as LRCK would have gone High.
