PCM5121: Simple setup for DAC output (no DSP)

Hello Philip, 

Some customers want to avoid Having an SCK as the DAC is geographically far away, or the noise of that clock would cause some kind of EMI failure. Data sheet explains when you want to use PLL:  Using the PLL means that only 3-wire digital communication is used, so the highest frequency is the BCK.  The 3-wire source reduces the need for a high frequency SCK,In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied. In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK. 

This is a common problem that can be avoided if you follow the recommended values in tables related setting the clk tree in figure 63.

Regards,

Arash

Hi,

sorry for the delay but I didn't get the usual email telling me that someone had responded to my question...

If I understand you correctly, the chip should work with it's default register values after reset, provided I am supplying valid clocks to LRCLK and BCLK ?

I am providing 192 kHz sqaure wave to LRCLK and 12.288 MHz square wave to BCLK which according to table 33 is valid but I'm getting nothing out of the analog output pins. The signal to DIN is I2S and it represents a -10dBFS 1kHz sinewave.

figure 63. is a little confusing as it does not show what values should be put into the various registers so is it possible for you to list the relevant registers and what value they should have in them?

thank you

PhilipJ

Hello, you have to be very careful about setting up the registries. I don't have the samples handy but from data sheet you need to follow these steps:

Table 133 is the recommended clock divider settings for PLL as Master Clock (in VCOM Mode). please use the values in this table to configure the registers listed in Table 34. (PLL Configuration Registers)

 Please also note the mapping in table 133 and table 34 (for example MDAC in table 133 is the value of DDSP in table 34, NDAC is the value of  DACCK, NCP is the value of CPCK and DOSR is the value of OSRCK.)  Please also note for correct operation DOSR must be chosen such that MOD fS / DOSR = 16 ( Refer to Table 36). The PLL coefficient  itself (from table 133)  can be written to PLL registers in table 35.

Regards,

Arash

Hi Arash,

thank you for the information.

I am slightly tied up on another project at the moment but I will try your suggestions as soon as I can. It may be a few days before I can report back on results.

Regards

Philip

Okay. Good luck.

Regards,

Arash

Hi Aresh,

I was reading the datasheet for PCM512x/4x EVM User's Guide (SLAU444A) and saw reference to a graphical setting program named CodecControl for managing this board but the link in the PDF leads to an Error 404 page.

I have used a similar CodecControl program for PCM9211 and it helped to work out what the IIC registers should be set to for a particular scenario.

Does the PCM512x CodecControl program still exist ? and if so could you post a link to find it ? or possibly upload it to here ? It might help me work out what to set the IIC registers to for a non-SCLK environment.

thanks

PhilipJ

Hello,

I found out from other posts that PCM5122EVM uses the same software as the PCM5102EVM, it can be found here.

https://www.ti.com/tool/PCM5102EVM-U

I hope this solves your issue.

Regards,

Arash

Hi thanks for the link, I downloaded it but unfortunately it didn't help. I had previously used the CodecControl implementation for PCM9211 which worked in "emulation" mode allowing one to set up the chip and then examine the data to see what it would have put into the chip's registers. Sadly the PCM512x version only seems to do anything if it finds the actual EVM board attached.

It would seem from what I can read from the chip that the analog outputs are muted (page 0 register 108 = 0x00) because there is a clock error reported. The PLL is reporting that it is locked (register 4 - 0x01) but beyond that I just can't seem to get the correct parameters setup for the clock(s) to be considered correct.

I have tried using auto-clock mode (register 37 bit 0x01) but this doesn't seem to help.

As mentioned previously, I am working with LRCK = 192 kHz and BCK = 12.288 MHz with no SCLK

Please could you ask your colleagues which registers need to be set and what values they should be set to. I will try attaching my Excel spreadsheet to this which highlights the registers and bits I have been "fiddling" with to try and get this chip to work.

Many thanks for your continuing support help

PhilipJ

Sorry but I couldn't find a way to upload a file for you to see my spreadsheet

PhilipJ