TAS5733L: TAS5733L

Entwicklung Glück-industrie

Part Number: TAS5733L

Hi,

we are now quite some time failing to startup the TAS5733L Amplifier without having it set the error register bit for overcurrent/undercurrent or temperature fault, although everything we can measure seems within recommendations, so we would appreciate very much any help and pointers!

Layout looks like this, we can measure i2s at 3.078Mhz when we do stream after startup sequence, we do measure 3.3V / 12V and do adhere to the minimum wait times depicted in TI datasheet document.

So we are probably complying with the necessary clock rates (mclk "faked" by connecting to SCLK).

We exported Configuration from PP3 application, and are simply applying it trying to adhere to the datasheet by placing trim oscillator and an appropriate wait time at the top instead of the order that comes from the PP3 export (where trim is called in the middle of config settings).

cfg_reg registers[] = {

// -----------------------------------------------------------------------------

// Initialization Sequence

// -----------------------------------------------------------------------------

{ 0x06, 0x07 }, // soft mute _> tried with and without this commented out, to no avail

{ 0x05, 0x40 }, // all-channel shut down to enable setup

// -----------------------------------------------------------------------------

// Amplifier Configuration

// -----------------------------------------------------------------------------

{ 0x1b, 0x00 }, // oscillator trim register must be run after each reset of device, 0x00 is factory preset but should pick up other values automatically anyway

{ CFG_META_DELAY, 50 },

{ 0x03, 0xa0 }, // system ctrl = PWM high-pass enabled (dc blocking) + soft unmute after clk error

{ 0x04, 0x05 }, // 24bit i2s => 16bit i2s would be 0x03

{ CFG_META_BURST, 3 }, // writing 0x0110 to register 0x07 (master volume)

{ 0x07, 0x01 },

{ 0x10, 0x00 },

{ CFG_META_BURST, 3 }, // writing 0x00c0 to register 0x08 (channel 1)

{ 0x08, 0x00 },

{ 0xc0, 0x00 },

{ CFG_META_BURST, 3 }, // writing 0x00c0 to register 0x09 (channel 2)

{ 0x09, 0x00 },

{ 0xc0, 0x00 },

{ CFG_META_BURST, 3 }, // writing 0x00c0 to register 0x0a (slew rate where is this in the docs ?)

{ 0x0a, 0x00 },

{ 0xc0, 0x00 },

{ 0x0e, 0xf0 }, // writing 0xf0 to register 0x0e (slew rate)

{ 0x10, 0x01 }, // modulation limit register to default 98.4% what does this mean? ???????????????

{ 0x11, 0xb8 }, // interchannel delay ch 1

{ 0x12, 0x60 }, // interchannel delay ch 2

{ 0x13, 0xa0 }, // not interchannel delay ch 1

{ 0x14, 0x48 }, // not interchannel delay ch 2

{ 0x19, 0x30 }, // PWM shutdown register a bit set to 1 means that channel is NOT STARTED with exit shutdown cmd => 0x30 == all channels should exit shutdown and play

{ 0x1a, 0x68 }, // start/stop period register to reduce pops and clicks at start-up and shutdown

// { 0x1b, 0x00 }, // oscillator trim register must be run after each reset of device, 0x00 is factory preset but should pick up other values automatically anyway

// { CFG_META_DELAY, 50 * 1000}, // wait and oscillator where here

{ 0x1c, 0x57 }, // BKND_ERR register, sets wait time before attempting restart of power stage on internal power stage errors to 1496ms

{ CFG_META_BURST, 5 }, // modulation scheme and routing to internal channels, this has 32bits width 0x00897772 ???????????????????????????????????????????????????????

{ 0x20, 0x00 }, // channel 1 bd mode, sdin-L to channel 1, channel 2 bd mode, sdin-R to channel 2 | remainder reserved 0x81 would be ad mode for chan 1

{ 0x89, 0x77 }, //

{ 0x72, 0x00 },

{ CFG_META_BURST, 5 }, // PWM output mux register 0x01021345 ??????????????????????????????????????

{ 0x25, 0x01 }, // first byte ok reserved | channel 1 to AMP_OUT_A + channel 1 to AMP_OUT_B + channel 2 to AMP_OUT_C + channel 2 to AMP_OUT_D | last byte reserved

{ 0x02, 0x13 },

{ 0x45, 0x00 },

{ CFG_META_BURST, 21 }, // these are fine-tuning settings for "bq"

{ 0x26, 0x00 },

{ 0x7f, 0x0e },

{ 0x41, 0x07 },

{ 0x01, 0xe3 },

{ 0x7d, 0x00 },

{ 0x7f, 0x0e },

{ 0x41, 0x00 },

{ 0xfe, 0x1a },

{ 0xba, 0x07 },

{ 0x81, 0xe1 },

{ 0xb5, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x27, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x28, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x29, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2a, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2b, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2c, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2d, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2e, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x2f, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x30, 0x00 },

{ 0x7f, 0xf0 },

{ 0xd7, 0x07 },

{ 0x00, 0x1e },

{ 0x53, 0x00 },

{ 0x7f, 0xf0 },

{ 0xd7, 0x00 },

{ 0xff, 0xe1 },

{ 0xab, 0x07 },

{ 0x80, 0x1e },

{ 0x51, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x31, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x32, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x33, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x34, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x35, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x36, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x37, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x38, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 }, // config fine tuning

{ 0x39, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 9 }, // config fine tuning

{ 0x3b, 0x00 },

{ 0x07, 0x60 },

{ 0x53, 0x00 },

{ 0x78, 0x9f },

{ 0xac, 0x00 },

{ CFG_META_BURST, 9 }, // config fine tuning

{ 0x3c, 0x00 },

{ 0x00, 0x00 },

{ 0x6d, 0xff },

{ 0xff, 0xff },

{ 0xe5, 0x00 },

{ CFG_META_BURST, 9 }, // config fine tuning

{ 0x3e, 0x00 },

{ 0x07, 0x60 },

{ 0x53, 0x00 },

{ 0x78, 0x9f },

{ 0xac, 0x00 },

{ CFG_META_BURST, 9 }, // config fine tuning

{ 0x3f, 0x00 },

{ 0x00, 0x00 },

{ 0x6d, 0xff },

{ 0xff, 0xff },

{ 0xe5, 0x00 },

{ CFG_META_BURST, 5 }, // config fine tuning

{ 0x40, 0x08 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 }, // config fine tuning

{ 0x41, 0x08 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 9 }, // config fine tuning

{ 0x42, 0x00 },

{ 0x00, 0x00 },

{ 0x6d, 0xff },

{ 0xff, 0xff },

{ 0xe5, 0x00 },

{ CFG_META_BURST, 5 }, // config fine tuning

{ 0x43, 0x08 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x44, 0x07 },

{ 0x21, 0x48 },

{ 0x2b, 0x00 },

{ CFG_META_BURST, 9 },

{ 0x45, 0x00 },

{ 0x00, 0x00 },

{ 0x6d, 0xff },

{ 0xff, 0xff },

{ 0xe5, 0x00 },

{ CFG_META_BURST, 5 }, // AGL CONTROL = AGL 1 to 4 all turned on, all other bytes reserved

{ 0x46, 0x00 },

{ 0x02, 0x00 },

{ 0x0f, 0x00 },

{ CFG_META_BURST, 9 }, // AGL Softening Filter

{ 0x47, 0x00 },

{ 0x07, 0x60 },

{ 0x53, 0x00 },

{ 0x78, 0x9f },

{ 0xac, 0x00 },

{ CFG_META_BURST, 9 }, // AGL Softening Filter

{ 0x48, 0x00 },

{ 0x07, 0x60 },

{ 0x53, 0x00 },

{ 0x78, 0x9f },

{ 0xac, 0x00 },

{ CFG_META_BURST, 5 }, // PWM Switching Rate Control Register SRC = 8 ?????????????????????

{ 0x4f, 0x00 },

{ 0x00, 0x00 },

{ 0x08, 0x00 },

{ CFG_META_BURST, 5 }, // Bank switching cmd

{ 0x50, 0x0f },

{ 0x70, 0x80 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 13 }, // output mixer

{ 0x51, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x07 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 13 }, // output mixer

{ 0x52, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x07 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x56, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x57, 0x00 },

{ 0x02, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x58, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x59, 0x00 },

{ 0x00, 0x0c },

{ 0x27, 0x00 },

{ 0x00, 0x18 },

{ 0x4f, 0x00 },

{ 0x00, 0x0c },

{ 0x27, 0x00 },

{ 0xf6, 0x23 },

{ 0xa6, 0x07 },

{ 0x89, 0xab },

{ 0xbc, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5a, 0x00 },

{ 0x59, 0x0c },

{ 0xdc, 0x07 },

{ 0x4d, 0xe6 },

{ 0x47, 0x00 },

{ 0x59, 0x0c },

{ 0xdc, 0x00 },

{ 0xab, 0x0d },

{ 0xc1, 0x07 },

{ 0xc6, 0xda },

{ 0x4f, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5b, 0x00 },

{ 0x03, 0x85 },

{ 0xfc, 0x00 },

{ 0x07, 0x0b },

{ 0xf8, 0x00 },

{ 0x03, 0x85 },

{ 0xfc, 0x00 },

{ 0xab, 0x0d },

{ 0xc1, 0x07 },

{ 0xc6, 0xda },

{ 0x4f, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5c, 0x00 },

{ 0x7b, 0x1d },

{ 0xfa, 0x07 },

{ 0x09, 0xc4 },

{ 0x0b, 0x00 },

{ 0x7b, 0x1d },

{ 0xfa, 0x00 },

{ 0xf6, 0x23 },

{ 0xa6, 0x07 },

{ 0x89, 0xab },

{ 0xbc, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5d, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5e, 0x00 },

{ 0x00, 0x0c },

{ 0x27, 0x00 },

{ 0x00, 0x18 },

{ 0x4f, 0x00 },

{ 0x00, 0x0c },

{ 0x27, 0x00 },

{ 0xf6, 0x23 },

{ 0xa6, 0x07 },

{ 0x89, 0xab },

{ 0xbc, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x5f, 0x00 },

{ 0x59, 0x0c },

{ 0xdc, 0x07 },

{ 0x4d, 0xe6 },

{ 0x47, 0x00 },

{ 0x59, 0x0c },

{ 0xdc, 0x00 },

{ 0xab, 0x0d },

{ 0xc1, 0x07 },

{ 0xc6, 0xda },

{ 0x4f, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x60, 0x00 },

{ 0x03, 0x85 },

{ 0xfc, 0x00 },

{ 0x07, 0x0b },

{ 0xf8, 0x00 },

{ 0x03, 0x85 },

{ 0xfc, 0x00 },

{ 0xab, 0x0d },

{ 0xc1, 0x07 },

{ 0xc6, 0xda },

{ 0x4f, 0x00 },

{ CFG_META_BURST, 21 },

{ 0x61, 0x00 },

{ 0x7b, 0x1d },

{ 0xfa, 0x07 },

{ 0x09, 0xc4 },

{ 0x0b, 0x00 },

{ 0x7b, 0x1d },

{ 0xfa, 0x00 },

{ 0xf6, 0x23 },

{ 0xa6, 0x07 },

{ 0x89, 0xab },

{ 0xbc, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x70, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x71, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x72, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x73, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x74, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x75, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x76, 0x00 },

{ 0x00, 0x00 },

{ CFG_META_BURST, 5 },

{ 0x77, 0x00 },

{ 0x80, 0x00 },

{ 0x00, 0x00 },

};

After this we wait 300ms before issuing 0x00 to 0x05 register for exit shutdown and write 0x0c00 or values yielding lower volume levels to master volume register and set soft mute register.

We can see all bits correctly travelling on the i2c bus on an oscilator and reading registers let's us conclude, the TAS5733L has set them as desired.
Nevertheless, we do never hear any sound, nor can we see the 0x02 error register at 0x00 - it is always with the second bit set as 0x02.

If needed we can also send an image of the oscilator showing the timing of pins nRST, nPDN, 3V3 and 12V, but they should be complying absolutely with datasheet requirements (always maintaining minimum times and low/high barriers).

over 2 years ago

0 Luis Fernandes de Pina over 2 years ago

TI__Genius 14420 points

Hello,

Can you provide the startup waveforms? Additionally, can you confirm what resistors are populated on the output for R714-718 on your board. If you disconnect from the output filter are you still seeing this fault triggered?

Is this seen on multiple boards? If you resolder a new IC on your board are you seeing this same issue?

best regards,

Luis

0 Entwicklung Glück-industrie over 2 years ago in reply to Luis Fernandes de Pina

Prodigy 10 points

Hi, Louis - will be back in a few minutes with a screenshot of the startup waveform and the resistor info. We do see the same fault on multiple boards, but did not try to resolder a new IC until now. For some more info - we are on a Linux system, so very very tight time contraints would put us into a bad situation, but I don't think this should be the problem at all in the end, also we have (due to having big condensators on the 12V line) a non-zero base-line for the PVDD but it's always a good chunk below the 6V mentioned in the datasheet. We also tried with that line starting at 0 to no avail. Maybe that one (pics are coming in next post) though could be the "interesting" one because it ramps up quite slowly and in steps.

0 Entwicklung Glück-industrie over 2 years ago in reply to Entwicklung Glück-industrie

Prodigy 10 points

Hi, we tried first to disconnect from the output filter - it seems this is definetely related, we can start the amp without further modification in software now and the error register stays at zero. We will now try to add piece by piece back on the pcb and report back at which point we'll get the error back.

0 Entwicklung Glück-industrie over 2 years ago in reply to Luis Fernandes de Pina

Prodigy 10 points

After we disconnected the Output Filter the error was gone. So we looked further into it. We Changed the application to work in Stero mode. In that mode we also had no error and also could play music through Channel A and B.

This led us to the solution PBTL mode could not be recognized. We looked again into our Application and found Resistor R703 to be too high with its 100kR. We reduced it to 42kR and finaly the error was gone and the Amp also worked in PBTL mode.

We totaly overlooked that the High Level input current of the digital Inputs could drain up to 75uA.

Thank you for your help. The hint with the output Filter led us to the right solution.

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TAS5733L: TAS5733L