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TAS2563: TAS2110 replaced with TAS2563 plays buzzing sound

Maciej Kaczkowski
Prodigy 20 points
Part Number: TAS2563
Other Parts Discussed in Thread: TAS2110, TAS2564

I've been using TAS2110 in my design for a while. It works fine. Last year it became unavailable, so my product upgraded to TAS2563, which seems to by pretty compatible with the former one. Unfortunately, new boards don't work properly. The sound is correct, but occasionally a buzzing is heard together with the sound.

Most settings are default. Working parameters are: 22,222 ksamples/s, 16bits/sample, 2 time slots. That gives SBCLK/FSYNC=32. Chapter 8.4.2 of Data sheet doesn't indicate this as allowed value, however it is supported by PPC3 software. I use AUTO_RATE detection and TDM_DET register reports proper value (0x02). No errors are reported.

Are there any special setting or conditions required by TAS2563 to work properly?

Regards

  • 0
    TI__Guru* 98235 points

    Hi Maciej,

    Could you provide some more details to help you debug?

    • Did you redesigned for TAS2563 QFN or WCSP?
    • Can you share some scope capture or recording of the observed buzzing?
    • What is the I2C configuration you're setting the device during initialization? I would not recommend to use the exact same as TAS2110.
    • Could you try by just sending these couple commands through I2C?
      • software reset -> write 0x01 into register 0x01 from book 0 page 0
      • change to active mode -> write 0x0c into register 0x02 from book 0 page 0

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 20 points
    •  QFN, mounted on the same board, as TAS2110.
    • I have not a scope image of the signal at the moment. I'll try to send it later.
    • Actually I have the same I2C connection in both versions. What do you mean by different configuration? The device address is the same: 0x4C, clock rate 100kHz.
    • That is what I do before programming. I even perform a hardware reset before configuration (followed by a delay).

    Can you confirm, that 22.2 ksamples/s is acceptable? I don't know what are PLL holding ranges.

    Thank you for help.

  • 0 in reply to Maciej Kaczkowski
    TI__Guru* 98235 points

    Hi Maciej,

    Maciej Kaczkowski said:
    That is what I do before programming. I even perform a hardware reset before configuration (followed by a delay).

    Can you try without programming? Just send software reset and power up commands, you can do hardware reset as well. The device should automatically detect the sampling rate and clock ratio so these commands should tell if it's working.

    If you have TAS2563QFN app on PPC3 I would suggest to better create a new configuration for this device, instead of using TAS2110 configuration.

    I have tested 22.2kHz before and it was working using the EVM.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 20 points

    we have a temporary provision of the problem. In out device, the amplifier works with NRF52 microcontroller with embedded bluetooth. The sound distortion disappears if bluetooth advertising is switched off. Apparently there is some interference between BT and TAS2564.

    As I mentioned before, our PCB was originally designed for TAS2110. There is a difference between TA2110 and TAS2563 reference guidelines. The IOVDD and VDD are connected together in the former one and separately in the later one. Could it be cause of our problems?

    PS. Here is a sample of distorted tone: https://mega.nz/file/ZWZTBQLJ#Hy_ThG_GKdqBKSP6-dhr49YRn2UoZXenQhVZ0rlc_JE

    Regards

  • 0 in reply to Maciej Kaczkowski
    TI__Guru* 98235 points

    Maciej,

    Do you mean VDD and IOVDD are shorted and connected to the same supply on TAS2563 as opposed to TAS2110 that only has VDD and no IOVDD?

    These devices may have similar pin distribution, but they're not fully compatible, for example how are you managing I2C address pins?

    Perhaps a lack of good decoupling on VDD or IOVDD is adding to the distortion issue, you should have individual decoupling as close as possible to the device for all internal and external voltage references like DREG, VDD, etc.

    I couldn't access to your attachment, I'll try again later using a different network.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 20 points

    Can you provide further guidelines on VDD/IOVDD connection? I have single power supply for both. How long separate paths on PCB? What kind of decoupling to separate pins properly. Ideally you could provide (fragment of) PCB of your development board.

    Thanks for your help

  • 0 in reply to Maciej Kaczkowski
    TI__Guru* 98235 points

    Hi Maciej,

    Ideally you should connect the power pins in star connection, if using the same source. The idea behind this is to isolate any ripple caused from one of the supplies to couple into the other power pin. You can send a friend request so that we can send private messages, I can share Gerber files over there if that helps.

    Schematic and PCB layer plots are available from User Guides:

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 20 points

    Out PCB is pretty compact - 2,5 x 4cm. So the connections are very short. Do you recommend serial inductors?

    What should be the distance form pins to common voltage regulator? Our PCB has separate layer providing supply for whole electronics. Now I know this is wrong. Your PCBs have separate connections for all power pins. Which pin, VDD or IOVDD is more sensitive to interference? We could provide separate V-regulator if necessary.

    With Regars

  • 0 in reply to Maciej Kaczkowski
    TI__Guru* 98235 points

    Hi Maciej,

    Serial inductors is a common practice, you can consider that.
    Distance to the voltage source can be considered as lower priority as long as the stability of the voltage is good at the pin, that's why we suggest to have good decoupling with 1 small capacitor for high frequency filtering and 1 bigger cap to work as charge reservoir for supply variations.

    Best regards,
    -Ivan Salazar
    Applications Engineer