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PCM4202 works in the PCM Slave Mode Operation or PCM master Mode Operation. I found that quad Rate Mode (LRCK=200KHz,SCKI= 128FS,BCK= 64FS) had high noise, while other modes had low noise.Figure 1 shows the corresponding FFT diagram.
Hi,
Are you changing sampling modes while keeping power on? Sometimes changing sample rates can cause noise issues without a proper power cycle. Also can you share a schematic of your setup?
Thank you,
Jeff
hi,jeff!
We tried the following two methods, but none of them worked.
1. Set the sampling mode before power on.
2. After changing the sampling mode, apply a low level to the RST pin for more than 65536 system clock cycles to force the PCM4202 to enter the power-down state.Then apply a high level to the RST pin.
What are the timings sent into the chip? For example with fs=192khx the Sclk is 36.6Mhz.Is there a 22 ohm series resistor in series with the clock near the source? Sometimes clock reflections can cause improper function.
hi,sanjay !
We have changed the series resistor in series with the clock near the source from 100Ω to 22Ω。And the timings sent into the chip is as follows : SCLK=25Mhz BCK=SCLK/2 LRCK=BCK/64 (Vcc=5.0V, VDD=3.0V,). The noise is still there.
Regards!
Can you please fry Fs=192k and 128*fs=24.576Mhz for Quad mode. These are multiples of 48K.
You can try slave mode. Just feed BCK as 12.288Mhz and LCK =192k
We have tried slave mode(BCK=64LRCK,LRCK=192k) without supporting the SCLK to the PCM4202. unfortunately, there is no output data from the pin 15.
Hi,
The PCM4202 requires an SCLK input in slave mode to operate correctly.
Best regards,
Jeff