Original question:
TLV320ADC5120: under AVDD=IOVDD=1.8V the left and right channel THD+N have big difference
TLV320ADC3120 power supply 1.8V, set to single-ended input mode, 10 kΩ input impedance, HPF setting 0.00025fs, input 2.5v peak-to-peak, 1.25v bias sine wave signal,
The ADC can normally sample the sine wave without distortion, which is inconsistent with the 0.5v RMS input range described in the manual under the 1.8V power supply. The following are the time domain and spectrograms during the test.
Hey Wu,
What is the vref of your ADC? if it is at 1.375V, then it can support analog signals from 0.5Vrms single-ended signal and 1Vrms differential signal with 1.8V AVDD. The bias_cfg register can configure your vref to support the appropriate analog signal range. The ADC5120 is designed to receive 0.5Vrms full-scale single-ended inputs, seeing yours is 2.5Vpp (0.8Vrms), allow me till next week to replicate this test and figure out why your single-ended input is not clipping past the intended single-ended input range. While I work on this, here is a table from the datasheet that refers to the AVDD and VREF modes.
Regards,
Ore.
Hey Wu,
If your reference voltage is very high, it might be high enough to support a 2.5Vpp signal. My previous response pointed to the modes to support single ended signals when AVDD=1.8V. If you configure your VREF to 1.375V and keep your input signal at 2.5Vpp, it would clip your signal. I have attached an image that shows clipping of 2.5Vpp with a vref at 1.375.
I hope this was able to help.
Ore.
