TLV320DAC3203: Maximum BCLK value for TDM Application

Cassio Berni

Part Number: TLV320DAC3203

Hi,

I need to use TLV320DAC3203 in TDM mode, slave, SR = 96 kHz, and the master device will generate a frame with 256.fs, i.e., bclk = 24,576 MHz. The reason for that high blck frequency is because the master device carries 8x slots of 24/32 bits different audio sources. The offset resource in TLV320DAC3203 allows me to select the desired source.

In TLV320DAC3203 documentation, blck_min_hi_period and bclk_min_low_period = 35 ns, which gives a maximum frequency of about 14,3 MHz.

Is there any form to accomplishes that issue, other than reducing SR to 48 kHz?

Thanks a lot, regards,
Cassio

over 1 year ago

0 Ivan Salazar over 1 year ago

TI__Guru** 100835 points

Hi Cassio,

As you mentioned, based on the spec I wouldn't rely on the device being able to support a higher clock rate. I assume your system requires all 8 channels operating in the same bus? Otherwise, you may consider reducing the number of slots thus reducing the clock rate.
Just to double check the device performance at higher clock rate, we can plan to run some tests with the EVM next week, although this is not a full device char or verification, would that be OK regardless?

Best regards,
-Ivan Salazar
Applications Engineer

0 Cassio Berni over 1 year ago in reply to Ivan Salazar

Prodigy 10 points

Hi, Ivan,

Yes, the system will need 8 to 10 channels in the tdm frame, same bus.

Ok, i appreciate the effort by testing higher clock rate with the EVM, i'll wait your results.

Thanks a lot, kind regards.

0 Ivan Salazar over 1 year ago in reply to Cassio Berni

TI__Guru** 100835 points

Hi Cassio,

OK, I'll keep you posted on any progress regarding this test over the next week.

Best regards,
-Ivan Salazar
Applications Engineer

0 Cassio Berni over 1 year ago in reply to Ivan Salazar

Prodigy 10 points

Hi, Ivan,

Did you get some results with the EVM board tests?

Thanks again!

0 Ivan Salazar over 1 year ago in reply to Cassio Berni

TI__Guru** 100835 points

Hi Cassio,

Apologies for the delayed response.
Unfortunately I'm currently out of office on business travel, I'll complete the testing and get back to you early next week.

Best regards,
-Ivan Salazar
Applications Engineer

0 Ivan Salazar over 1 year ago in reply to Ivan Salazar

TI__Guru** 100835 points

Hi Cassio,

After testing this in the lab, I could verify the device is not able to support the suggested higher clock rate. So the conclusion is that you may have to reduce the sampling rate or number of channels to reduce the clock rate.

Best regards,
-Ivan Salazar
Applications Engineer

0 Cassio Berni over 1 year ago in reply to Ivan Salazar

Prodigy 10 points

Hi, Ivan,

Ok. I'll adequate the design.

Thanks a lot, best regards.

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TLV320DAC3203: Maximum BCLK value for TDM Application