Other Parts Discussed in Thread: TLV320DAC3203
Hi Ivan,
I am back here with the question about shut-down of the TLV320DAC3203.
It is said in SLAU434A:
The DAC Modulator is clocked by DAC_MOD_CLK. For proper power-up of the DAC Channel, these clocks must be enabled by configuring the NDAC and MDAC clock dividers ( Page 0,Register 11, D(7) = 1 and Page 0, Register 12, D(7) = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shut-down. During this shut-down sequence, the NDAC and MDAC dividers must not be powered down, or else a proper low power shut-down may not take place. The user can read the power-status flag in Page 0, Register 37, D(7) and Page 0, Register 37, D(3). When both flags indicate power-down, the MDAC divider may be powered down, followed by the NDAC divider.
The is clocked by DIG_MIC_CLK. For proper power-up of the ADC Channel, these clocks are enabled by the NADC and MADC clock dividers (Page 0,Register 18, D(7) = 1 and Page 0, Register 19, D(7) = 1). When the ADC channel is powered down, the device internally initiates a power-down sequence for proper shut-down. During this shut-down sequence, the NADC and MADC dividers must not be powered down, or else a proper low power shut-down may not take place. The user can read the power-status flag in Page 0, Register 36, D(6) and Page 0, Register 36, D(2). When both flags indicate power-down, the MADC divider may be powered down, followed by NADC divider.
- This sequence should be initiated by the Host?
- What happens, if for some reason, a proper low power shut-down not take place?
- Would a reset do the job?
- Is there some example code to follow I might have missed?
Have a nice WE!
Best regards,
Gustavo