TLV320ADC6140: No AREG, no I2S DATA

Rafal Szymecki

Prodigy 10 points

Part Number: TLV320ADC6140

Hello TI team,

I'm working with TLV320ADC6140 with 2 single ended electret mic lines.

ADC is used in slave 1/2 channel 48kHz 32bit

Im not getting any data on the scope. I noticed that the AREG and MICBias has no voltage.

DREG is at 1.45v, Supplying 3.3V to analog and 1.8V to digital IO

IRQ pin is high but I believe I disabled that. I do measure 48.035KHz on analyzer. Would that put create bus error?

sl_sleeptimer_delay_millisecond(5);
  ADC_Write(I2C0,0x01,0b00000001); // Reset registers
  sl_sleeptimer_delay_millisecond(10);
  ADC_Write(I2C0,0x02,0b10001001); // Sleep Reg - Internal 1.8V Areg, 10ms, not sleep
  sl_sleeptimer_delay_millisecond(10);
  ADC_Write(I2C0,0x07,0b01110000); // ASI I2S 32bit Auto CLK
  sl_sleeptimer_delay_millisecond(10);
  ADC_Write(I2C0,0x08,0b00000000); //
  ADC_Write(I2C0,0x09,0b00100000); // 1 Disable Error detection

  ADC_Write(I2C0,0xA, 0b00010000); // Mixing No mix, -6dB, No inversion
  ADC_Write(I2C0,0xB, 0b00000000); // Slot 0 ch1
  ADC_Write(I2C0,0xC, 0b00000000); // Slot 0 ch2
  ADC_Write(I2C0,0xD, 0b00000000); // Slot 0 ch3

  ADC_Write(I2C0,0x13,0b00000111); // Slave automatic PLL
  //ADC_Write(I2C0,0x14,0b10001000); // not used in slave mode
  //ADC_Write(I2C0,0x15,0b10000010); // Read Only but 44.1-48 1:32 ratio BLCK FSYNC
  //ADC_Write(I2C0,0x16,0b00001000); // CLK_SRC when in Master

  ADC_Write(I2C0,0x21,0b00100101); // GPIO setup Interrupt
  ADC_Write(I2C0,0x22,0b00000001); // IN2M_GPO1 disabled act low
 // ADC_Write(I2C0,0x29,0b10000000); // Interrupt GPIO1 as GPO
  ADC_Write(I2C0,0x2B,0b00000000); //

  ADC_Write(I2C0,0x32,0b00000000); // INT ACtive high
  ADC_Write(I2C0,0x33,0b00000000); // Masking interrupt
  ADC_Write(I2C0,0x36,0b11100000); // Interupt config ASI PLL MIX Int
  ADC_Write(I2C0,0x3A,0b01100000); // Common Mode avdd peak
  ADC_Write(I2C0,0x3B,0b00000001); // IN2M Bias 2.5v
  //ch1
  ADC_Write(I2C0,0x3C,0b00100000); // CH1 setup Mic Single AC 2.5k DREoff
  ADC_Write(I2C0,0x3D,100); // CH1 Gain
  ADC_Write(I2C0,0x3E,100); // CH1 volume
  ADC_Write(I2C0,0x3F,0b10000000); // CH1 gain calibration
  //ch2
  ADC_Write(I2C0,0x41,0b00100000); // CH2 setup Mic Single DC 2.5k DREoff
  ADC_Write(I2C0,0x42,100); // CH2 Gain
  ADC_Write(I2C0,0x43,100); // CH2 volume
  ADC_Write(I2C0,0x44,0b00010000); // CH2 gain calibration

  ADC_Write(I2C0,0x6B,0b00100001); // DSP DRE HPF
  ADC_Write(I2C0,0x6C,0b00000000); // DSP clipping, volume control,
  //ADC_Write(I2C0,0x6D,0b00100000); // DRE config Dynamic Range Enhance
  //ADC_Write(I2C0,0x70,0b00100000); // AGC config Automatic Gain Control

  ADC_Write(I2C0,0x73,0b01000000); // Channel enabling input, EN1 En2

  ADC_Write(I2C0,0x74,0b01000000); // Channel enabling output, En1 En2

  ADC_Write(I2C0,0x75,0b11110000); // Power controls
  //ADC_Write(I2C0,0x76,0b11000000); // ADC power up
  //ADC_Write(I2C0,0x77,0b11100000); // Active mode

9 months ago

0 Daveon Douglas 9 months ago

TI__Genius 15060 points

Hi Rafal,

Before analyzing your script, lets ensure HW is correct, correct clocks, and power is provided to device. Can you provide comments on the following points:

For single-ended configuration, please implement one of the following circuit connections at input:

We also recommend pulling up SDA/SCL to IOVDD in I2C, but if writes to device are successful i supposed okay for now.
For your clocks, your confirming 48Khz status on FSYNC? What is the BCLK frequency?
MICBIAS is dc coupled to GND in your schematic so there will be no voltage?

Regards,

0 Rafal Szymecki 9 months ago in reply to Daveon Douglas

Prodigy 10 points

Hi Dave,

Sorry for bad schematic. Inputs are AC coupled and I2C is lifted to 1.8V.

BCLK hovers between 2.91MHz-3.333MHz, FSYNC 47.985KHz- 48.031KHz, analyzer shows errors.

I though I could measure 2.5V on MicBias pin that's going to the mics.

Thank you

0 Daveon Douglas 9 months ago in reply to Rafal Szymecki

TI__Genius 15060 points

Hi Rafal,

I believe there is an ASI bus clock error. Device is in slave mode, 32-bit wordlength, the BCLK should = (32-bit WL, 2Ch, 48KHz Fs) 3.072Mhz stable, 6.144Mhz-4Ch, Frame clock input should also be a stable 48KHz.

Please provide stable clocks and this preset configuration below:

# CHECKSUM 0
# Generated by ADCx140EVM-SW v3.0.5
# TLV320ADC5140 device configuration
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 98 00 00
# Reset Device
w 98 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select Page 0
w 98 00 00
# Wake up and enable AREG
w 98 02 81
# Clock Error Disable/Enable
w 98 04 40
# GPI Configuration
w 98 3b 60
# Channel 1 configuration
w 98 3c a0
# Channel 2 configuration
w 98 41 a0
# Channel 3 configuration
w 98 46 a0
# Channel 4 configuration
w 98 4b a0
# Channel Input/Output Configuration
w 98 74 f0
w 98 1e 82
# M divider Enabled with Divider Value
w 98 1f c0

Also make sure schematic follows structure of typical application in 9.2.1 of d/s.

Regards,

Audio

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TLV320ADC6140: No AREG, no I2S DATA