SRC4392EVM-PDK: software issues

The following sequence should be used to initilaize SRC4392.

1. Apply power and external reset.

2. Write all control registers on Page 0 except register 0x01.

3. Apply MCLK, as well as any audio clocks desired for Ports A and B.

4. Write register 0x01 on Page 0 to power up the desired blocks.

5. Disable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 1.

6. Write 0x02 to register 0x7F to set Page 2 as the active page.

7. Write data to the DIT C and U buffers on Page 2 as desired.

8. Write 0x00 to address 0x7F to set Page 0 as the active page.

9. Enable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 0. 
This will update the DIT TA buffer with the data written to Page 2 registers.

Example for Implementation of above:

1. External reset

2. Setting control registers on page 0 (it's always register address first, then data [all values in hex])

  w e0  7f 00      //Set Register Page 0
  w e0  03 20      // I²S Port A: Clock Slave, 24 Bit Audio MSB, Output Signal from Receiver - NOT from SRC
  w e0  04 00      // I²S  Port A: MCLK Source = MCLK; MCLK Freq = 128x LRCLK (MCLK Freq other than 128x just for Master Mode operation)
  w e0  07 00      // Clock Start Output; Transmitter MCLK Divider == FPGA CLK / 128
  w e0  09 01      // Transmitter Channel State Update via SPI
  w e0  0d 00      // Receiver Input == RX1, Ref CLK RXCKI (ext.)
  w e0  0E 00      // Receiver Mute if No CLK, Superclock on ext. Pin, CLK Divider = 4
       // Receiver PLL Ref Clk according Data Sheet (Table 4, S.60)
  w e0  0F 22   
  w e0  10 00    
  w e0  11 00  
       //
  w e0  2D 02      // SRC Source == Receiver, ref. CLK FPGA

3. Enable clock  (mclk, frame sync, sample clock)

4.  w e0  01 37  // switch on SRC, Receiver, Transmitter, I²S Port A


Here is the script for steps 5 to 9:


w e0 08 08 // disable the DIT buffer transfer

w e0 7f 02 // set page to 2

w e0 2e ee // write ee to reg 2e on page 2

w e0 2f ff //write ff to reg 2f on page 2

w e0 7f 00 //change the page back to 0

w e0 08 00 // enable the DIT buffer transfer

w e0 7f 02 // switch back to page 2

r e0 2e 01 // read back reg 2e on page 2

r e0 2f 01 // read back reg 2f on page 2

w e0 7f 00 // set page to page 0

# This code file  assumes a 24.576MHz master clock and then sets up Ports A and B for 96kHz 24 bit I2S output (master mode).  
# This script will probably need to be tweaked some, but it should provide a good starting point. 
# One thing to note is the MCLK reference chosen for Ports A and B and the DIR is "MCLK" pin, this may need to be changed to "RXCKI" depending on the application.  
# When feeding the TAS and PCM devices make sure the MCLK for those devices is synchronous to the BCLK / WCLK being fed to them.

2)  There is not set clock, I chose MCLK assuming that the MCLK pin will be fed with a clock. 

3)  By writing register 0x01, you can power down different sections of the SRC individually for lower-power, without having to reset all the registers (pg 51 of the d/s).


# RESET RESET THIS IS MASTER RESET FOR SRC (48kHz)

# Page 0 = DEFAULT for Control

# Write to page 0

#

w E0 7F 00

# Register 01, Bit 7 = 1 resets to default

d 100

w E0 01 80

# Delay 0.1 sec to allow part to reset

d 100

# Register 01, Bit 7 = 0 for normal operation

w E0 01 00

d 100

# w E0 7F 00

 

# Register 01, Bit 7 = 1 resets to default

#----- Setup Port A/B ------#

# 24bit I2S, Master mode, DIR source, at mute

# Divide by 256, MCLK input source

#

w E0 03 69
w E0 04 01

w E0 05 69
w E0 06 01
 

#----- Setup DIR ------#

#DIR Config 1

# Input source: RX2 - S/PDIF RCA (default)

#w E0 0D 09

# Input source: RX4 - S/PDIF optical, RX_MUX = RX1

w E0 0D 08

 

#DIR Config 2 - default

w E0 0E 01

 

#----- Setup DIT -----#

# DIT COnfig 1

# Port A data in, DIv 256

w E0 07 80

 

# DIT Config 2

# Default is to output to RCA

# Commment out RCA and uncomment Optical for optical outputs

 

#Output to RCA

# TX - ON, TX MUTE - ON, Optical disabled

#w E0 08 06

# TX Mute - OFF

#w E0 08 04

 

#Output to Optical

# TX - OFF, TX MUTE - ON, optical disabled

w E0 08 03

# TX MUTE - OFF

w E0 08 01

 

#----- PLL Configuration -----#

# Set P=2, J=8, D=0

w E0 0F 22

w E0 10 1B

w E0 11 A3

 

# GPIO1 Config

# GPIO1 = RCVR non-audio data

w E0 1B 06

 

# GPIO2 Config

# GPIO2 = RCVR non-valid data

w E0 1C 07

 

# Power Status

# Disable RCVR (/PDRX) and Port B(/PDPB) power down and enable All Function power down

#w E0 01 14

 

# Unmute Port A/B Output

w E0 03 29
w E0 05 29

 

# Disable All Function power down (all blocks set by local control)

w E0 01 3F