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TAC5212: 0.5 Vrms full-scale swing with AVDD=3.1V

Bernhard Boehmer
Expert 1060 points
Part Number: TAC5212

Hello TI,

1. We have a requirement to (non-concurrently) support two full-scale modes: 1 Vrms [around 1.65 VDC common mode] (line 1 in the table below) as well as 0.5 Vrms [around 0.9 VDC common mode] (line 3 in the table below).




We assume that an internal LDO generates Vref from AVDD. Question: Is the "1.7 V to 1.9 V" in the table above a hard requirement, or would it be possible to generate Vref = 1.375 V from an AVDD of 3.1V? i.e. Is it possible to supply AVDD=3.1 V to the part and still support 0.5 Vrms full-scale input swing around 0.9 VDC (similar to DAC side of TLV320AIC32x4 / TLV320AIC32x6)?

2. Similar to above, but on output / DAC side: Is it possible to supply AVDD=3.1 V to the part and still support 0.5 Vrms full-scale output swing around 0.9 VDC (similar to TLV320AIC32x4 / TLV320AIC32x6)?

3.When is the next update of the datasheet expected?

  • 0
    TI__Mastermind 28400 points

    Hi Bernhard,

    Unfortunately we are limited to the combinations above since the AVDD/VREF relationship defines the input swing. However you could use digital gain to artificially change where the full scale limit is. In your example you want a 0.5Vrms input swing when the part has a 1Vrms input swing. By adding 6dB of gain to the channel, the ADC would hit fullscale at 0.5Vrms. Same approach applies to the DAC side.

    I'm not sure when the datasheet is expected, but I've notified on of our product marketing engineers to see if they have an ETA on a datasheet update.

  • +1 in reply to Jeff McPherson
    TI__Mastermind 28400 points

    Hi Bernhard,

    I checked with our team and there is a datasheet update expected in around April. If you have questions that the datasheet currently doesn't answer please let us know so we can be sure to include it.

    Thank you,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Expert 1060 points

    Hello Jeff,

    Thank you for the update. Adding 6 dB of digital gain would reduce the SNR by 6 dB, correct?

    We are hoping that the next datasheet will show that 0.9 V common mode will be possible from AVDD = 3.1V, especially on the TAC5212 outputs. Some single-ended designs are eased if a particular common mode voltage can also be incorporated as part of the subsequent amplification stage without having to rebias. My expectation is that the TAC5212 does actually support the abovementioned operating point in hardware.

  • 0 in reply to Bernhard Boehmer
    TI__Mastermind 28400 points

    Hi Bernhard,

    Yes it would reduce SNR by 6dB. Thanks for the info on your requirement. I'll pass this on to our design team and I will let you know if there's a workaround.

    Best regards,
    Jeff McPherson