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Original question:

PCM3168A: only has four output with TDM8 mode

PCM3168A: PCM3168 interface with ADSP BF527

Arvind Khalate
Prodigy 40 points
Part Number: PCM3168A
Other Parts Discussed in Thread: PCM3168

Hi,

We are replacing CS42436 with PCM3168A

We are using ADSP BF527 SPORT for TDM data.

Codec is in slave Mode and operating in single speed mode (SSM)

please can you help on physical interface between PCM3168A and ADSP BF527

Thanks & Regards,

Arvind Khalate

  • 0
    TI__Mastermind 27085 points

    Hi Arvind,

    For TDM data, the codec requires a 3 wire I2S interface (FSYNC, BCLK, and DATA) as well as a synchronous system clock SCKI to run the internals of the device. If you're running both the ADC and the DAC, there will be an additional DATA line, adding up to 5 total clock/data connections. Additionally the DAC and ADC can be run with different interfaces/sample rates if desired using the xAD/xDA pins.

    I'm not an expert on the ADSP BF527 since it's not a TI device, but at a quick glance of the datasheet, you would set both SPORTs to transmit FSYNC/BCLK/and DIN (to the codec) and receive DOUT (from the codec).

    Let me know if you have any other questions.
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Thank you Jeff for reply

    Below red marked pins are available on PCM3168 Codec,  is FSYNC/BCLK referring to LRCKAD/DA and BCKAD/DA?

    As per data sheet of codec in the case of TDM data format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 pins are used

    Please can you confirm if below connection are ok.

    ADSP TF0 >> PCM3168A- LRCKAD/DA

    ADSP TSCLK0 >> PCM3168A- BCKAD/DA

    PCM3168A- DOUT1>> ADSP, DR0PRI

    ADSP, DT0PRI  >> PCM3168A- DIN1

    SCKI is connected to external 11.28MHz CO

    Thanks 

    Arvind

  • 0 in reply to Arvind Khalate
    TI__Mastermind 27085 points

    Hi Arvind,

    Yes FSYNC refers to LRCKAD/DA and BCLK is BCKAD/DA. Also those connections look correct to me.

    The tricky part is your external crystal oscillator. We don't recommend having a master clock external to the I2S host since frequency drift will cause dropped frames and audio sync issues. See this app note for more detail: https://www.ti.com/lit/an/slaa469a/slaa469a.pdf

    A better solution would be for the ADSP to give the SCKI. If that is not possible, the other option is for the PCM3168A to become the I2S host, and its clocks will be received by the ADSP rather than transmitted by the ADSP to the codec. Data direction would remain the same. 

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff,

    Thank you

    In master mode, as per schematic below external crystal oscillator connected to codec and Processor.

    same configuration do we need to use?

    Thanks & Regards,

    Arvind Khalate

  • 0 in reply to Arvind Khalate
    TI__Mastermind 27085 points

    Hi Arvind,

    That would be the right way to include the external crystal as SCKI input.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff,

    I noticed you mentioned Ti don't recommend having a master clock external to the I2S host since

    We are planning to use TDM format  24-bit left-justified mode TDM not I2S mode TDM

    Can we use external clock to Codec and codec in slave mode.

    Regards,

    Arvind Khalate

  • 0 in reply to Arvind Khalate
    TI__Mastermind 27085 points

    Hi Arvind,

    Sorry for the confusion. I was using I2S as a generic term. Our recommendation applies to all TDM/I2S formats including 24-bit LJ TDM.

    Best regards,
    Jeff McPherson