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Original question:

TLV320AIC3120: Headset Detection Functionality clarification

TLV320AIC3120: TLV320AIC3120: Headset Detection

Akilarasan R
Prodigy 210 points
Part Number: TLV320AIC3120

Hi,

We are trying to do headset jack detection functionality in TLV320AIC3120. We are following below steps:

  1. Configured 0x88 in Page 0 / Register 67 (0x43) - To enable headset jack detection
  2. Configured 0x81 in Page 0 / Register 48 (0x30) - To enable INT1
  3. Configured 0x15 in Page 0 / Register 51 (0x33) - To get interrupt at GPIO1 pin

We observed that headset jack detection is happening by reading 0x43. But, we didn't get any interrupt at GPIO1 pin. Is there any other configuration needs to be done?

One more thing, We configured 0x15 in Page 0 / Register 51 (0x33) where D0 bit is configured as 1. Is that means, GPIO pin will give high output in the event of interrupt?

  • 0
    TI__Mastermind 26235 points

    Hi Akilarasan,

    What are the values that you configured each register with? D0 in 0x33 is redundant as long as the pin isn't configured as a general purpose value (0011 or 0010). Have you tried also reading 0x2C to see if the interrupt flag is being set by headset detection?

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    Hi Jeff,

    We are configuring 0x88 in 0x43, 0x81 in 0x81register and 0x15 in 0x33 register. Should we have to configure 0011 in D5-D2 bit of 0x33 to get gpio output. 

    We want to get interrupt signal at gpio pin. Is there a way I can do it?

  • 0 in reply to Akilarasan R
    TI__Mastermind 26235 points

    Hi Akilarasan,

    No, D5-D2 should be 0101 as you have it. What is the value read from 0x2C when a headset is inserted?

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    Hi Jeff,

    When headset is not inserted, value read at 0x2C is 0x0 and when headset is inserted, value read at 0x2C is 0x10.

  • 0 in reply to Akilarasan R
    TI__Mastermind 26235 points

    Hi Akilarasan,

    I'll be able to test this tomorrow and let you know if there's a setting missing.

    Thank you,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    TI__Mastermind 26235 points

    Hi Akilarasan,

    The EVM didn't support the testing I was hoping to get. Can you share your schematic and full register map so I can see the issue at a higher level?

    Also what sequence are you taking to test the headset detection? If the register is read before you monitor GPIO, the GPIO will clear.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    Hi Jeff,

    Below attached images are our schematic

    Then we are doing following configurations:

    1.Configured 0x88 in Page 0 / Register 67 (0x43) - To enable headset jack detection

    2.Configured 0x81 in Page 0 / Register 48 (0x30) - To enable INT1

    3.Configured 0x15 in Page 0 / Register 51 (0x33) - To get interrupt at GPIO1 pin

  • 0 in reply to Akilarasan R
    Prodigy 210 points

    Hi Jeff,

    Also, please tell what configuration should I do for D0 and D1 bit of Page 0 / Register 51 (0x33).

  • 0 in reply to Akilarasan R
    TI__Mastermind 26235 points

    Hi Akilarasan,

    D0 and D1 are redundant since GPIO is set to INT1. I would leave them at 0. 

    How are you measuring GPIO? Are you monitoring in real time to see an event? If you try to read the register and then look at GPIO, the interrupt will clear and you will see nothing.

    Another debugging step you can take is to try to set INT1 to a different interrupt type and see if that works. That may give a clue as to where the issue is.

    Thank you,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    Hi Jeff,

    We are probing GPIO signal with oscilloscope. We are getting 2 ms pulse but multiple pulses. Then we got to know whenever headset is inserted, headset insertion interrupt and PTT button press interrupt both are coming together causing multiple pulses. Now my doubt is

    1. Is there any way we can ignore PTT button press interrupt?
    2. Is Page 0 / Register 67 (0x43) a read clear register as it will get cleared once after reading?
  • 0 in reply to Akilarasan R
    TI__Mastermind 26235 points

    Hi Akilarasan,

    In register 0x31, make sure bit 6 is 0 to disable the button press interrupt. You can also set bit 0 to 0 to have only a single pulse rather than multiple pulses.

    Yes 0x43 is a live register and will not clear when read. The headset detection is monitored continuously. 

    Best regards,
    Jeff McPherson