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TLV320AIC3204: TLV320AIC3204 audio output with noise

?? ?
Prodigy 10 points
Part Number: TLV320AIC3204

Hi team，

Here's an issue may need your help:

We encountered an issue when using the TLV320AIC3204 DAC chip. Whether playing audio through HPL/R or LOL/R, there will be noise. Specifically manifested as:

1. Playing 0.5kHz audio will generate 15.5kHz and 16.5kHz noise. (see attached spectrogram)

2. Playing 1kHz audio will generate 15kHz and 17kHz noise.

3. Playing 2kHz audio will generate 14kHz and 18kHz noise.

This IC is how we use it:

Send a 0.5kHz/1kHz/2kHz sine signal with a sampling rate of 16KHz and a 16bit depth to a MCU via USB audio interface,

After converting the sound into 32 bit depth, the MCU sends it to the DAC via i2s. The MCLK is 24.576 mhz, the LRCLK is 16 kHz, and the BCLK is 1.024 mhz

The dac configuration is as follows:

// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
aic3204_reg_write(AIC3204_CODEC_IF, 0x20)
We would like to know why this noise occurs. Could you please help us analyze the cause? Thank you.

Best Regards,

Linus

  • 0
    TI__Mastermind 28885 points

    Hi,

    Can you provide your configuration? 

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 10 points

    Hi,

    Here is our config code.

    // Set register page to 0
aic3204_reg_write(AIC3204_PAGE_CTRL, 0x00) == 0 &&

// Initiate SW reset (PLL is powered off as part of reset)
aic3204_reg_write(AIC3204_SW_RST, 0x01) == 0 &&

// Program clock settings
// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
// Power up NDAC and set to 1
aic3204_reg_write(AIC3204_NDAC, 0x81) == 0 &&
// Power up MDAC and set to 4
aic3204_reg_write(AIC3204_MDAC, 0x84) == 0 &&
// Power up NADC and set to 1
aic3204_reg_write(AIC3204_NADC, 0x81) == 0 &&
// Power up MADC and set to 4
aic3204_reg_write(AIC3204_MADC, 0x84) == 0 &&
// Program DOSR = 128
aic3204_reg_write(AIC3204_DOSR, 0x80) == 0 &&
// Program AOSR = 128
aic3204_reg_write(AIC3204_AOSR, 0x80) == 0 &&
// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
aic3204_reg_write(AIC3204_CODEC_IF, 0x20) == 0 &&
// 
aic3204_reg_write(54, 0x02) == 0 &&
aic3204_reg_write(32, 0x00) == 0 &&
// Program the DAC processing block to be used - PRB_P1
aic3204_reg_write(AIC3204_DAC_SIG_PROC, 0x01) == 0 &&
// Program the ADC processing block to be used - PRB_R1
aic3204_reg_write(AIC3204_ADC_SIG_PROC, 0x01) == 0 &&
// Select Page 1
aic3204_reg_write(AIC3204_PAGE_CTRL, 0x01) == 0 &&
// Enable the internal AVDD_LDO:
aic3204_reg_write(AIC3204_LDO_CTRL, 0x09) == 0 &&

//
// Program Analog Blocks
// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
aic3204_reg_write(AIC3204_PWR_CFG, 0x08) == 0 &&
// Enable Master Analog Power Control
aic3204_reg_write(AIC3204_LDO_CTRL, 0x01) == 0 &&
// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
aic3204_reg_write(AIC3204_CM_CTRL, 0x33) == 0 &&
// Set PowerTune Modes
// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
aic3204_reg_write(AIC3204_PLAY_CFG1, 0x00) == 0 &&
aic3204_reg_write(AIC3204_PLAY_CFG2, 0x00) == 0 &&
// // Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-D driver.
// aic3204_reg_write(AIC3204_PLAY_CFG1, 0xC0) == 0 &&
// aic3204_reg_write(AIC3204_PLAY_CFG2, 0xC0) == 0 &&
// Set ADC PowerTune mode PTM_R4.
aic3204_reg_write(AIC3204_ADC_PTM, 0x00) == 0 &&
// Set MicPGA startup delay to 3.1ms
aic3204_reg_write(AIC3204_AN_IN_CHRG, 0x31) == 0 &&
// Set the REF charging time to 40ms
aic3204_reg_write(AIC3204_REF_STARTUP, 0x01) == 0 &&
// HP soft stepping settings for optimal pop performance at power up
// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
aic3204_reg_write(AIC3204_HP_START, 0x25) == 0 &&
// Route Left DAC to HPL
aic3204_reg_write(AIC3204_HPL_ROUTE, 0x08) == 0 &&
// Route Right DAC to HPR
aic3204_reg_write(AIC3204_HPR_ROUTE, 0x08) == 0 &&
//Route Left DAC to LOL
aic3204_reg_write(0x0e, 0x08) == 0 &&
//Route Right DAC to LOR
aic3204_reg_write(0x0f, 0x08) == 0 &&
// Unmute HPL and set gain to 0dB
aic3204_reg_write(AIC3204_HPL_GAIN, 0x00) == 0 &&
// Unmute HPR and set gain to 0dB
aic3204_reg_write(AIC3204_HPR_GAIN, 0x00) == 0 &&
// Unmute LOL and set gain to 0dB
aic3204_reg_write(0x12, 0x00) == 0 &&
// Unmute LOR and set gain to 0dB
aic3204_reg_write(0x13, 0x00) == 0 &&
// Unmute Left MICPGA, Set Gain to 0dB.
aic3204_reg_write(AIC3204_LPGA_VOL, 0x00) == 0 &&
// Unmute Right MICPGA, Set Gain to 0dB.
aic3204_reg_write(AIC3204_RPGA_VOL, 0x00) == 0 &&
//Power up HPL and HPR, LOL and LOR drivers
aic3204_reg_write(AIC3204_OP_PWR_CTRL, 0x3C) == 0
// Wait for 2.5 sec for soft stepping to take effect
aic3204_wait(2500);
//
// Power Up DAC/ADC
// Select Page 0
aic3204_reg_write(AIC3204_PAGE_CTRL, 0x00) == 0 &&
// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
// DAC Vol control soft step 1 step per DAC word clock.
aic3204_reg_write(AIC3204_DAC_CH_SET1, 0xd4) == 0 &&
// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
aic3204_reg_write(AIC3204_ADC_CH_SET, 0xc0) == 0 &&
// Unmute Left and Right DAC digital volume control
aic3204_reg_write(AIC3204_DAC_CH_SET2, 0x00) == 0 &&
// Unmute Left and Right ADC Digital Volume Control.
aic3204_reg_write(AIC3204_ADC_FGA_MUTE, 0x00) == 0

    Best Regard

    Linus

  • 0 in reply to ?? ?
    TI__Mastermind 28885 points

    Hi,

    Based on your settings above, they do not match what you described above.

    The settings are configured to be 48KHz with 24-bit word length, but your description is for 16KHz with 16- or 32-bit depth.

    That's why you are seeing the other tones as the sampling is 48KHz instead of 16KHz.

    My suggestion is to change the following in your settings:

    Change NDAC/MDAC to 2 and 6 as shown above and the word-length to 32-bit word length (B0_R27 to 0x30) since your BCLK is 64x16KHz=1.024 MHz.

    May I know what's your company and the use case?

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 10 points

    Hi,

    Thank for your help, we have solved this problem. I'm an electronics engineer for Seeed Studio, and this case is an audio development board.

    And our software engineer found an issue that if the Headphone is set to use the class d driver, the Lineout background noise will be increased. Could you please help us analyze the issue? 

    Best Regard

  • 0 in reply to ?? ?
    TI__Mastermind 28885 points

    You can read more for HP in class-D mode in this reference guide section 2.3.3.4.

    TLV320AIC3204 Application Reference Guide

    If noise in LINEOUT, maybe your supply or there's coupling to your line output.