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TAS5631 startup timing

SteveCrump
Mastermind 18510 points
Other Parts Discussed in Thread: TAS5631

A customer posted the following questions about TAS5631 startup.

We turn on the PWM/AMP chips for about 120mS and send a 4500Hz tone for about 70ms during the 120mS interval.  We repeat this roughly every 2 seconds.  We use the PWDN and RESET pins of the PWM/AMP chips to do this.  This works very well.

However, we would like to power down PVDD between the 120mS intervals to minimize power dissipation.  We have tried this with a delay of about 50mS before enabling TAS5631, but the startup time at VI_CM with the standard 4.7uF cap is much longer than 50mS, so the pulse is distorted.

Can we vary the caps at VI_CM and/or PSU_REF to speed up startup to less than 50mS, to avoid the distortion?  Is there any other means of doing that?

Is it normal for VI_CM to take this time to settle?

 

An immediate answer is that we will consider this and see if there is a way to accomplish the customer's goal.

Best regards,

Steve Crump.

  • 0
    TI__Guru**** 189399 points

    Steve,

    Any update?

    -d2

  • 0
    TI__Mastermind 18510 points

    It is normal for VI_CM in a standard EVM circuit to take around a second to settle when PVDD is turned on.  It is also possible to shorten VI_CM startup time, but doing so is very likely to introduce pop or click.  The severity of the pop or click depends on the increase in startup speed.

    The customer can evaluate this by reducing C.VI_CM times 1/2, 1/4, 1/8.  If the pop or click is acceptable for the application there is no problem in doing this. 

    Best regards,

    Steve.