TLV320AIC3120: Not able to test Audio-Loopback and Beep Generator

Hi,

You are configuring the path to take ADC output and loop it back to DAC, but your ADC clock configurations are not set.

Here is an example for both ADC and DAC for the PLL configurations to get 16KHz sampling.

Once this is set, send a tone from your MIC and see the output is heard.

Another thing I noticed; you are using external Clock OSC for MCLK.

For slave mode, this is not recommended. In master mode, you should use the same clock to the host as shown in the apps. note below.

Audio Serial Interface Configurations for Audio Codecs (Rev. A)

I'm not sure what you intend to do with the beep? I suggest you first try the loopback above.

Regards.

Right now I only need to generate different beeps for user notifications, in the future I will need the capability to record and play audio.

I have tried these settings too, but it is still not working. following is the update code I'm using.

static const tlv_cmd_t init_cmd[] = {
    {0x00, 0x00}, // Page 0
    {0x01, 0x01}, // sw reset
    // PLL config
    {0x04, 0x03}, // Clock-gen Mux. PLL_CLKIN=MCLK, CODEC_CLKIN=PLL_CLK
    {0x05, 0x91}, // PLL P+R. PLL power up, P=1, R=1 (P=divider,R=multiplier)
    {0x06, 0x06}, // PLL J = 6
    {0x07, 0x27}, // PLL D fractional. D-value MSB = 0x27
    {0x08, 0x10}, // PLL D fractional. D-value LSB = 0x10
    // mode master
    {0x1B, 0x0C}, // mode is i2s master, wordlength is 16, BCLK/WCLK out
    // divider configs
    {0x0B, 0x87}, // NDAC is powered up and set to 7
    {0x0C, 0x86}, // MDAC is powered up and set to 2
    {0x0D, 0x00}, // DOSR = 384 0x180, DOSR(9:8) = 0x01
    {0x0E, 0x80}, // DOSR = 384 0x180, DOSR(7:0) = 0x80
    {0x12, 0x87}, // NADC divider is powered down and ADC_DSP_CLK = DAC_DSP_CLK.
    {0x13, 0x86}, // MADC divider is powered down and ADC_MOD_CLK = DAC_MOD_CLK.
    {0x14, 0x80}, // AOSR = 256 0x100, AOSR(7:0) = 0
    //
    {0x74, 0x00}, // DAC => volume control thru pin disable
    {0x44, 0x00}, // DAC => drc disable, th and hy
    {0x41, 0x00}, // DAC => 0 db gain left
    //
    {0x00, 0x01}, // Page 1
    {0x21, 0x4E}, // De-pop, Power on = 800 ms, Step time = 4 ms
    {0x1F, 0x84}, // HPL
    {0x23, 0x40}, // LDAC routed to HPL
    {0x28, 0x0E}, // HPL unmute and gain 1dB
    {0x24, 0x00}, // No attenuation on HP
    {0x25, 0x00},
    {0x2E, 0x0A}, // MIC BIAS = 2.5v
    {0x30, 0x40}, // MICPGA P = MIC M 10K
    {0x31, 0x10}, // MICPGA N = MIC N 10K
    //
    {0x00, 0x00}, // Page 0
    {0x3C, 0x0B}, // select DAC DSP mode 11 & enable adaptive filter
    //
    {0x00, 0x08},
    {0x01, 0x04},
    //
    {0x00, 0x00},
    {0x3F, 0x96}, // POWERUP DAC (soft step disable)
    {0x40, 0x04}, // Unmute DAC
    {0x51, 0x80}, // Powerup ADC channel
    {0x52, 0x00}, // Unmute ADC channel
    //
    {0x00, 0x01},
    {0x2A, 0x1C}, // Unmute Class-D left
    {0x20, 0xC6}, // Power-up Class-D drivers
};

static const tlv_cmd_t loop_back_cmd[] = {
    {0x00, 0x00}, // Page 0
    {0x1d, 0x1d}, // b4 = ADC-to-DAC loopback enabled
    {0x00, 0x01},
    {0x2e, 0x0a}, // MICBIAS = 2.5V
    {0x26, 0x4c},
};

I am also wondering if there could be an issue with the schematic.
for e.g. we left the RESET line floating and was not able to communicate with the host via I2C, we pulled it high and now I2C communication is working.
But we do not know if there is still some issue there

When first ramping up AVDD, IOVDD and DVDD, reset pin is pulled low and when the supplies are stable then release it (pull high to IOVDD).

Don't leave it floating.

See section 7.3.2.

Few things to check:

• WCLK and BCLK are giving the correct and stable frequencies
• Once the clocks are correct, you can check the recording path first without loopback. Provide the tone for your mic, add gain if necessary.
• Once the recording works, then apply the loopback.

I have modified the setting from the one you sent above. This is for loopback and without additional gain on HP/Class-D output.

Setting ADC-DAC loopback

Regards,