PCM5121: PLL configuration for 312.5kHz sampling rate

morten simonsen

Prodigy 10 points

Part Number: PCM5121

Dear TI,

My hardware produce the following signals to a PCM5121 in I2C, slave mode:

* 32-bit Left Adjusted, two's complement L/R audio samples at 312.5kHz

* LRCK at 312.5kHz

* BCK at 20MHz (64*Fs)

* SCK at 40 MHz (128*Fs)

I have not been able to obtain a useful analog output in this mode, initially trying with the PLL off. Now, I suspect (the datasheet really is exceptionally poor - regretfully) that the internal detectors might be so closely tied to standard audio rates that the autoconf (PLL off) might not function at Fs = 312.5kHz - for this reason, I now try to configure the PLL...

In relation to this, It is not clear to me, from the datasheet, the required clock rates. Figure 62 says that the DACCK is 128Fs (my 40MHz SCK directly), but most examples from the datasheet seems not to go higher than around 6.144MHz for the DACCK; the objectives that need to be accomplished by the PLL setting is not clear to me by reading the datasheet.

Can you possibly help me either by directly giving me the objectives I need to fulfill in order to make it work at this rate? - alternatively point me towards some documentation that explains the required conditions related to the clocking/PLL setting in more detail?

Thank you and best regards

Morten

P.S: I am quite in a hurry; this is only a small part of a large design - and I had never anticipated such small detail to be such an obstacle

2 months ago

0 Arash Loloee 2 months ago

TI__Mastermind 20870 points

Hello Morten,

the problem is coming from not using common audio clocks. In datasheet you read that : SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode by configuring various PLL and clock-divider registers.

Section 8.3.6.4 Clock Generation Using the PLL gives you the description and registers needed for setting up PLL.

Also section 8.3.6.5 PLL Calculation is the most important page for your calculations.

you can take a look at Table 131-136. Recommended Clock Divider Settings for PLL as a guide.

The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz.

I give you a sample calculation and you can expand on it. refer to Fig 63 so you can follow my calculations:

fs=312.5k PLLCK has to be an integer of fs, lets assume you want N=128 so PLLCLK has to be 128x312.5k=40.00MHz

lets say you are using BCK as the source of PLLCLKIN, so your PLLCLKIN=20MHz

now from equation PLLCLK= (PLLCLKIN*R*K)/R .

Lets say I choose R=1, P=1 ( I need to program them in the registers , which I will explain as well). So with PLLCLKIN and PLLCLK, R and P known, Khas to be 2.0 which means J=2 and D=0000 (note that in case your BCK is 20.02MHz, then your J and D will be different )

in case you are not familiar with how to program R, P, J and K to get my desired PLLCLK for a given PLLCLKIN.you can refer to this random example

**********************************************************************************************************

Lets say you want to program these values P=1 , J=8 , D=7075

Now we have to convert these decimal values to binary for register 20, 21, (22 and 23) 24 that is for programming PLL

(Refering to these registers , you see P is 4bits, J is 6 bits and D is 14 bits )

P is 4bit so P=1 means 0001, p3 p2 p1 p0

J is 6bit, so J=8 means 001000 , J5 J4 J3 J2 J1 J0

D is 14 bit, so D=7075 means 01 1011 1010 0011 in binary , D13 D12 D11...........D2 D1 D0

Now you need to program reg 22 with the above values for its corresponding bits 0 0 D13 D12 D11 D10 D9 D8, ( the 00 is reserved per datasheet)

and program register 23 with D7 D6 D5 D4 D3 D2 D1 D0

So reg 22 (hex 16) is 0001 1011 ==> write reg16==> 1B

and reg 23 (]hex 17) is 1010 0011 =write reg17==> A3

I think that should cover programming the PLL.

Regards,

Arash

0 morten simonsen 1 month ago

Prodigy 10 points

Dear Arash,

Thanks for your prompt reply. I believe that I managed to get it to operate. I have one observation though: The PLL keeps reporting unlocked; it does not seem to cause any bad behavior (I ignore the unlocked PLL detection in register 0:37) - furthermore I have directed the PLL/4 signal onto one of the GPIO's and when I compare it to my external SCK, they seem to be 100% locked in both phase- and frequency. My VCO frequency is 80MHz and the PLL REF is 10MHz - I think all should be within allowed ranges.

Could this PLL unlocked be a consequence of the non-audio standard sampling rate somehow? (or should I continue debugging/experimenting in order to get a condition where the PLL says locked?

Thanks again and br

Morten

0 Arash Loloee 1 month ago in reply to morten simonsen

TI__Mastermind 20870 points

Hi Morten,

It is good to hear that it is operating now,

As you know , this is an Audio DAC and thus has been tested extensively for common Audio frequencies. Your observation might be due to the non common frequency used, so if your external sck and PLL/4 signal are fully locked it should be ok, of course it is better if you have it reported lock .

I would let it work continuously for a while and let it go through several power up/down cycles and if always it comes back okay it should be fine.

Regards,

Arash

0 morten simonsen 1 month ago in reply to Arash Loloee

Prodigy 10 points

Hello Arash,

Thanks - and exactly what I have done (10 boards working with random power cycling, two of them in temperature chamber) - it seems that the PLL is locking reliably. So I guess I will not focus on the lock flag; it does really seem to lock deterministically and in perfect frequency lock (must be a second order PLL-loop as the phase is not drawn to zero-residue; but this does not matter; there are no cycle-slips).

Thanks for your help, br

Morten

0 Arash Loloee 1 month ago in reply to morten simonsen

TI__Mastermind 20870 points

Yes, with 10 board tested, i think it is okay.

Regards,

Arash

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PCM5121: PLL configuration for 312.5kHz sampling rate