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PCM5121: Volume control issue

PYTsai
Genius 9735 points
Part Number: PCM5121

Tool/software:

Hi 

My customer are using two pcs of PCM5121 on the same PCB. 

they do below setting first 

Reg 0x02 standby RQST=1

Reg 0x00 reset RSTM=1, RSTR=1

Reg 0x02 active RQST=0

and then they try to do volume control for both PCM5121. however only one PCM5121 can do volume control. the other one volume control not work. 

My customer found if they add ramp up speed delay 50 ms as below sequence. then they can successfully control the volume for both device. 

Reg 0x02 standby RQST=1

Reg 0x00 reset RSTM=1, RSTR=1

Reg 0x08(page1) ramp up fast speed Delay 50ms

Reg 0x02 active RQST=0

Can you provide the example for how to do volume control for two device on a same PCB ? thanks !

  • 0
    TI__Mastermind 20870 points

    Hello,

    The PCM512x has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be userdefined by the ADR1 and ADR0 terminals. The 4 possible addresses are 0x98, 0x9A, 0x9C and 0x9E. Each PCM512x responds when it receives its own slave address. So they have to make sure the address is correct for each IC on the PCB.

    As an example using ADR1 and  ADR2 of each device, you can set one to 98 and the other one to 9C and then you can write in each device separately. For example the follwoing two lines 

    w  98 01 00

    w  9C 01 11

    put all modules and registers in  device with address 98  in Normal mode , where as device with address 9C will be reset.

    Also I noted you mentioned Reg 00  in the above script , whereas on Page 0, the register that resets all modules and registers ( RTSM and RSTR )  is Reg 01 not Reg00  (Table 54. Page 0 / Register 1) . 

    Let me know if they still have any issue.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Genius 9735 points

    Hi Arash 

    Customer are using SPI mode(MODE1=High)，they use chip select (MS) to select the device to do programing. 

    Can you help check what else we missed? 

    thanks!

  • 0 in reply to PYTsai
    TI__Mastermind 20870 points

    Hello,

    The registers should be the same as above  for SPI or I2C,( such as  Page 1, Register 2, D4(L-ch) / D0(R-ch).  Same thing with Page 0 / Register 1.

    They need  to plot all  SPI signals  and monitor them for both devices, I suspect one of these signals might be the reason. Please refer to  Figure 71. Control Interface Timing and Table 37. Control Interface Timing.

    Also swap the two devices and see if the problem follows the device ( just to get a confirmation that a specific device is not the cause). 

    Once they have verified all the above, we can play with the 50ms they are adding , to see whether  some sort of delay is needed or a specific minimum delay is needed. That might give us a hint later but for time being I would verify the SPI signals per table 37.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Genius 9735 points

    Hi 

    Customer had verified SPI signal, they looks ok.

    The found, each DAC, they need to add 50 ms delay after reset commend to make each DAC work correctly.

    Is adding 50 ms right approach to solve this issue, or there might be something wrong ? 

  • 0 in reply to PYTsai
    TI__Mastermind 20870 points

    Hello, I don't see any problem with adding a delay to resolve the issue since it is not destructive, I just don't know the mechanism that it bypasses  the problem.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Genius 9735 points

    Hi Arash,

    Base on customer's experiment result, any idea why the issue happens ? Customer worry that adding a delay did not actually solve the issue, 

    or how do customer to confirm if the two device on the board are working correctly ?

  • 0 in reply to PYTsai
    TI__Mastermind 20870 points

    Hello,

    We need to do some debug to figure out the reason, as I have not seen this issue before. I suggested in my previous post to vary the 50ms and find the minimum delay needed. Also please screen capture all SPI related signals for both chips with and without delay . I suspect it has something to do with the routing of one of the DACs ( they already have verified when they swap the DACs, the DAC in the same location needs the delay, correct??).

    Also would you please send me the schematics and also the layout with the CS signal marked on the layout for a quick review.

    Regards,

    Arash