PCM6240-Q1: PCM6xx0 devices with TDM question

Hi Jack,

Please see this link (https://e2e.ti.com/support/audio-group/audio/f/audio-forum/450891/tlv320aic3254-dsp-and-tdm-mode ) which explains the difference between TDM and DSP mode well. This datasheet incorrectly uses them interchangeably when there are differences in the interface protocol. This device supports TDM interface in both slave and master mode.

You can adjust the data to output at the falling ede of FSYNC by adding an offset bit to the data line (TX_OFFSET=1) in page 0, register 8

hello Douglas,

the link you shared me looks the current page, not the correct link.  can you share again?

For second question, how i know SOC(Master) send the BCLK/FSYNC  meet ADC (Slave) TDM format requirement?

Test Result: Below is test result (ADC as TDM slave. register 7 setting 0X34;  register 8 setting 0x01 (TX_OFFSET=1) ;)

from test result, we know FSYNC change status when BCLK rising edge; Looks not meet datasheet requirement.

so should I setting  FSYNC change status when BCLK falling edge by SOC side to meet datasheet requirement?

Acceptance criteria from Datasheet

Hi Jack,

By default, FSYNC and each data bit is transmitted on the rising edge of BCLK. Your image shows data output on the falling edge of BCLK and FSYNC

Jack Jiang said:

coud i setting falling edge of FSYNC starts the data transfer?

Isn't this the objective?

You can try changing the FSYNC_POL, or add offset bits to help.

Regards,

Hello Douglas,

My question is not clear, let me clarify the point I want to express based on last reply.

let me enlarge image.my image shows data shift on the falling edge of BCLK ; but FSYNC shift on  the rising edge of BCLK ;

so   how i know SOC(Master) send the BCLK/FSYNC  meet ADC (Slave) TDM format requirement?

should i adjust FSYNC shift from  the rising edge of BCLK to  the falling  edge of BCLK;

Below is datasheet requirement:

Hi Jack,

Ok I understand, but yes please adjust FSYNC and BCLK to both change status at the rising edge or falling edge simultaneously. FSYNC and BCLK status must be in sync in this way

Figure 1: BCLK POL = 1; both at the falling edge

If you want TDM format to have both data transmit and FSYNC change status on the rising edge of BCLK:

Figure 2: BCLK_POL = 1, and TX_EDGE = 1; both at rising edge

hello Hello Douglas, 

is this mistype? i guess you want to say : both data change status and FSYNC change status on the rising edge of BCLK:

or   both data change status and FSYNC change status on the falling  edge of BCLK:

 Hello Douglas,

i set BCLK_POL = 1, and slot TX_OFFSET=1 ; the same configuration, why PurePath Console 3 show different result; looks amazing.

which is correct?  my point is A] is correct. what is your thinking?

A] if you create new project:

B] if you load  the project  

Then i further click "load present" button, then it will show the same format as A]

Jack Jiang said:

i guess you want to say : both data change status and FSYNC change status on the rising edge of BCLK:

or   both data change status and FSYNC change status on the falling  edge of BCLK:

Yes, sorry for not being clear. 

Jack Jiang said:

Then i further click "load present" button, then it will show the same format as A]

Your last image shows the preset configurations that we provide for easy evaluation it doesn't load your settings to the EVM. Any changes you make on the GUI become live when you press the "Active" button

In short, make changes for how you want the device to perform, then press Active if you are using EVM. You can do a register dump to a .cfg file on left hand tab

Jack Jiang said:

what is your thinking?

This is preference, either can be correct

hello Douglas,

 on my  hand, i have no EVM,  i only want to know correct ADC audio format if   setting according to below through PurePath Console 3,

then SW  can set corresponding Audio format in SOC TDM Master side to meet ADC slave TDM side audio format;

Also HW can easily put this PurePath Console 3 audio format as Acceptance criteria; 

PurePath Console  for PCM6240  setting below:

1、 4 channel differential AC line input;

2、BCLK_POL = 1, and slot TX_OFFSET=1;

so i think A]  should be correct audio format. Not B].  right?

Hello Douglas,

OK then i understand , thanks for your patient answer.