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Original question:

TLV320ADC6120: TLV320ADC6120 clock issue using internal LDO

TLV320ADC6120: TLV320ADC6120 clock issue using internal LDO

ben biles
Intellectual 850 points
Part Number: TLV320ADC6120

Tool/software:

Hi Sanjay , did you ever mange to try this on the an EVM ? 

I made another PCB design using the same part and I don't get any FSYNC clock at all.

I am using 24.576mhz oscillator MCLK on GPIO1 in master mode.

I am using internal LDO 1.8V and running IOVDD and AVDD on 3.3V

I would much appreciate it if you could try the EVM for this part and confirm that it is possible to use it in Bus Master mode with PLL active.

and if you get it to work , you could upload register settings and PP3 software file so I can try the settings on my hardware.

If I can't get the part to generate BCLK and FSYNC properly I will need to look at another vendor for a high dynamic range ADC

which would be a shame as I have to designs with this stumbling block.

 

  • 0
    TI__Genius 14360 points

    Hi,

    Many of our engineers are out of office this week, expect a response early next week.

    Thanks for your patience

  • +1 in reply to Daveon Douglas
    TI__Prodigy 670 points

    Hi,

    The following configuration was checked on EVM for these conditions:

    1) Master mode with 24.576MHz MCLK

    2) Fs = 48kHz, BCLK-to-Fs ratio = 256

    #Page 0
w 9c 00 00
w 9c 01 01  #SW Reset

#Page 0
w 9c 00 00
w 9c 02 81  #Wake up device, enable internal AREG

w 9c 13 87  #Master Mode, MCLK = 24.576MHz
w 9c 14 48  #Fs = 48kHz, BCLK-to-Fs = 256

w 9c 21 a2  #GPIO1 as MCLK

w 94 73 c0  #Enable CH1, CH2 inputs
w 9c 74 c0  #Enable CH1, CH2 ASI Outputs

w 9c 75 60  #Power Up ADC, PLL

    Thanks and Regards,

    Lakshmi Narasimhan

  • +1 in reply to Lakshmi Narasimhan Badrinarayanan
    Intellectual 850 points

    Hi Lakshmi ! 

    Thank you so much for taking the time to do this.

    I have the correct clocks working now using PLL and external MCLK in GPIO1

    It appears the order of register writes is crucial and also it was necessary for me to add delay between

    each write to the registers to get ACK on I2C.