Tool/software:
Hi team,
Page 46 of the datasheet describes the startup sequence.
The I2C clock input starts 5ms after PDN is set high, but there is no guarantee that the clock can be input in Stable from the beginning of the clock when the clock is supplied from Soc.
In step 4, it says Once I2S clocks are stable,~ so I can interpret this as "there can be a period of time when the clock is unstable", is this correct?
Periods when the clocks are unstable = "Periods when the amplitude and frequency of the clocks are not stable.
Regards,
Ryu.
