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TLV320AIC3254: MCLK/BCLK/WCLK and data is OK but no sound

Kevin Kim
Prodigy 10 points
Part Number: TLV320AIC3254

Tool/software:

The MCLK(12.288MHz)/BCLK(1.536MHz)/WCLK(48KHz) is supplied from imx8mp(NXP) and data transmittedto codec,  but there is no sound at playback.

The all clocks and data signal is OK.

We don't use external AVDD and DVDD (GND), but IOVDD 1.8V and LDOIN 3.3V only. Of course, LDO_SELECT pin is high(1.8V).

We refer to 4.0.2 In the TLV320AIC3254 Application Reference Guide((SLAA408A).

For our circuit using internal AVDD and DVDD rather than external, which register value have to changed? 

Are there any other registers that have to be set other than the below?

  - b[3]=0 in page 1 / register 1

  - b[0]=1 in page 1 / register 2

  - b[3]=1, b[0:1]=1 in page 1 / register 0x0a

  - b[3]=1 in page 1 / register 0x33 for capture, not playback

Thanks.

  • 0
    TI__Mastermind 28220 points

    Hi Kevin,

    Can you share the full script so that I can see where you have placed the writes in the sequence?

    Thank you,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 10 points

    I tested it in aic32x4_mute function using speaker-test -t wav command (sampling rate=48000, channel=1, S16_LE).

    There is no signal to ether HP or Line-out. The script is referred from example setups 4.0.2 in document  SLAA408A.

    static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
    {
    struct snd_soc_component *component = dai->component;

    /* HP detection enable (default=0x00)
    b[7] = enable
    b[5:6]=Read only : 01=strearo detect, 11=streao+cellular
    */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x43), 0x80);

    /* software reset (default=0x00)
    b[0] : self clearing software reset
    */
    // s/w reset in aic32x4_probe()
    // snd_soc_component_write(component, AIC32X4_REG(0, 0x01), 0x01);

    /* clock setting register 6 and 7 (default=0x01)
    b[7] : NDAC/MDAC divider power up
    b[0:6] : NDAC/MDAC value
    */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x0b), 0x81); // NDAC
    snd_soc_component_write(component, AIC32X4_REG(0, 0x0c), 0x84); // MDAC

    /* DAC OSR Setting */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x0d), 0x00); // MSB (default=0x00)
    snd_soc_component_write(component, AIC32X4_REG(0, 0x0e), 0x40); // LSB (default=0x80)

    /* DAC signal processing block control (default=0x01) : PRB_P1
    b[0:4] : DAC Signal Processing Block PRB_Px
    */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x3c), 0x08);

    /* power configuration register
    b[3] : use external or internal AVDD(default=00)
    0=internal AVDD
    1=external AVDD (disabled weak connection of AVDD with DVDD)
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x01), 0x00);

    /* LDO control (default=0x08)
    b[3] : analog block power control, (WRANING) 1=disable
    b[0] : AVDD LDO power up
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x02), 0x01);

    /* reference power up register (default=0x00), b[0:2]
    0=power up slowly when analog blocks are powered up
    1=power up in 40ms when analog blocks are powered up
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x7b), 0x01);


    /* Headphone Driver Startup Control (default=0x00),
    b[6:7]
    - 00 : Soft routing step time is 0ms (*)
    - 01 : Soft routing step time is 50ms
    - 10 : Soft routing step time is 100ms
    - 11: Soft routing step time is 200ms
    b[2:5]
    - 0000: Slow power up of headphone amp's is disabled
    - 1001 : 1001: Headphone ramps power up slowly in 5.0 time constants (*)
    b[0:1]
    - 00 : Headphone ramps power up time is determined with 25k resistance
    - 01: Headphone ramps power up time is determined with 6k resistance (*)
    - 10: Headphone ramps power up time is determined with 2k resistance
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x14), 0x25);


    /* (WARNING) internal AVDD/DVDD is used using LDOIN 3.3V, not use external AVDD/DVDD (default=0x00)
    b[6]
    - 0 : Full Chip Common Mode is 0.9V
    - 1: Full Chip Common Mode is 0.75V
    b[4:5]
    - 00 : Output Common Mode for HPL and HPR is same as full-chip common mode
    - 01: Output Common Mode for HPL and HPR is 1.25V
    - 10: Output Common Mode for HPL and HPR is 1.5V
    - 11: Output Common Mode for HPL and HPR is 1.65V if D6=0, 1.5V if D6=1
    b[3]=1 : LOL/R is 1.65V and is powered by LDOIN
    b[1]=1 : HPL/R is powered with LDOIN
    b[0]=1 : LDOIN 3.3V (1.8V ~ 3.36), 0=1.5V~1.95V
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x0a), 0x0b);


    /* HPL/R routing */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x0c), 0x08);
    snd_soc_component_write(component, AIC32X4_REG(1, 0x0d), 0x08);

    /* Playback Configuration Register (default=0x00)
    b[6:7]
    - 00 = LDAC routing to HPL uses Class-AB driver
    - 11 = LDAC routing to HPL uses Class-D driver
    b[2:4] : Left DAC PTM(Power Tune Mode) Control
    - 000 = Left DAC in mode PTM_P3, PTM_P4
    - 001 = Left DAC in mode PTM_P2
    - 010 = Left DAC in mode PTM_P1
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x03), 0x08); // LDAC in mode PTM_P1
    snd_soc_component_write(component, AIC32X4_REG(1, 0x04), 0x08); // RDAC in mode PTM_P1


    /* HP/Line output mute control
    b[6]=1(defult) -> mute
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x10), 0x00); // HPL
    snd_soc_component_write(component, AIC32X4_REG(1, 0x11), 0x00); // HPR
    snd_soc_component_write(component, AIC32X4_REG(1, 0x12), 0x00); // LOL
    snd_soc_component_write(component, AIC32X4_REG(1, 0x13), 0x00); // LOR

    /* HPL/R and LOL/R power up (default=0x00)
    b[4:5] : HPL/R power up
    b[2:3] : LOL/R power up
    b[1] : MAL(Mixer Amplifier Left) power up
    b[0] : MAR(Mixer Amplifier Right) power up
    */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x09), 0x3F/*0x3C*/);

    /* LOL/R routing */
    snd_soc_component_write(component, AIC32X4_REG(1, 0x0e), 0x0a/*0x08*/); // LDAC route to LOL : 0x0a=with MAL
    snd_soc_component_write(component, AIC32X4_REG(1, 0x0f), 0x0a/*0x08*/); // RDAC route to LOR : 0xa=with MAR

    /* DAC channel setup 1 : power control (default=0x14)
    b[7] : LDAC power up, default=0(power down)
    b[6] : RDAC poser up, default=0(power down)
    b[4:5] : LDAC data path control (defulat=01 : LDAC -> L channel)
    b[2:3] : RDAC data path control (default=01 : RDAC -> R channel)
    b[0:1] : Soft-Step volume control (default=00)
    */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x3f), 0xd6);

    /* DAC channel setup 2 : DAC mute control
    b[4:6] : DAC auto mute control
    b[3] : LDAC mute=1(default)
    b[2] : RDAC mute=1(default)
    */
    snd_soc_component_write(component, AIC32X4_REG(0, 0x40), 0x00); // 0x0C (mute)
    }

  • 0 in reply to Kevin Kim
    Prodigy 10 points

    Even if you change page 1 register 0x7b to 5 by referring to datasheet 2.9.1.1.1 standby mode(3.3V operation), the result is the same.