TLV320AIC3107: TLV320AIC3107

Tool/software:

I am playing audio ... but it turns out my BCLK was shorted to MCLK.  We fixed the short and now have no MCLK and therefore no audio.  I still have a BCLK.

So I think I just need to get MCLK running.

Here are the relevant codec / MCLK pieces from my device tree:

      sound-tlv320 {

           compatible = "fsl,imx-audio-tlv320";

           model = "imx-tlv320";

           audio-cpu = <&sai1>;

           audio-codec = <&tlv320aic3107_1>;

           audio-routing =

           "Speaker Positive",     "SPOP",

           "Speaker Negative",     "SPOM",

           "Speaker Positive",     "SWOUTP",

           "Speaker Negative",     "SWOUTM",

           "Headphone Jack",       "HPLOUT",

           "Headphone Jack",       "HPROUT",

           "Line Out Jack",        "LLOUT",

           "Line Out Jack",        "RLOUT",

           "LINE1L",               "Line In Jack",

           "LINE2L",               "Line In Jack",

           "LINE1R",               "Line In Jack",

           "LINE2R",               "Line In Jack";

     };

&i2c3 {

     clock-frequency = <100000>;

     pinctrl-names = "default";

     pinctrl-0 = <&pinctrl_i2c3>;

     status = "okay";

     tlv320aic3107_1: tlv320aic3107_1@18 {

           #sound-dai-cells = <0>;

           compatible = "ti,tlv320aic3007";

           reg = <0x18>;

           tdm-offset = <0>;

           gpio-reset = <&gpio1 15 GPIO_ACTIVE_LOW>;

           clocks = <&clks IMX7D_OSC_24M_CLK>;

           clock-names = "mclk";

           status = "okay";

           /* Regulators */

           ai3x-ocmv = <3>;

           IOVDD-supply = <&reg_3p3v>;     /* I/O Voltage */

           DVDD-supply = <&reg_3p3v>;      /* Digital Core Voltage */

           AVDD-supply = <&reg_3p3v>;      /* Analog DAC Voltage */

           DRVDD-supply = <&reg_3p3v>;     /* ADC Analog and Output Driver Voltage */

     };

};

&clks {

     assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

     assigned-clock-rates = <884736000>;

};

&sai1 {

     pinctrl-names = "default";

     pinctrl-0 = <&pinctrl_sai1>;

     assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,

                  <&clks IMX7D_SAI1_ROOT_CLK>;

     assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;

     assigned-clock-rates = <0>, <36864000>;

     status = "okay";

};

&iomuxc {

     pinctrl-names = "default";

      asc-imx7s {

            pinctrl_i2c3: i2c3grp {

                fsl,pins = <

                     MX7D_PAD_I2C3_SDA__I2C3_SDA      0x4000007f

                     MX7D_PAD_I2C3_SCL__I2C3_SCL      0x4000007f

                >;

           };

           pinctrl_sai1: sai1grp {

                fsl,pins = <

                     MX7D_PAD_SAI1_MCLK__SAI1_MCLK         0x1f

                     MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17     0x14

                     MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16     0x14

                     MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0  0x30

                     MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC   0x1f

                     MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK   0x1f

                     MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0  0x1f

                     MX7D_PAD_GPIO1_IO15__GPIO1_IO15       0x74

                >;

           };

     };

};

I’m wondering if you see anything wrong here related to MCLK?