PCM1795: Slow turn on behavior

Hi Abigail,

Would you  please provide more information including the schematics ,  waveforms for their clks, supplies and input/output as well.

This is a Current DAC and needs the conversion to voltage, so do they see the issue at the output of the DAC or after the I-V and diff to single conversion?

Regards,

Arash

Passing over the customer's answer: 

Hi Arash, 

I'm the customer Abi mentioned. We're using the PCM1795 in an audio amp, DAC and reconstruction filter are attached. 

We power up the system, start the clocks, take the DAC out of reset, don't do any configuration, then give it full scale signal and the output of the DAC ramps up to full.

the total ramp time to full output is more then 6 seconds. any idea what could be going on?

Attachments: 

Clocks

Ramp and turn on

Reset and Clocks

DAC Schematic

Hi Arash,

I'm the customer that Abi is posting for.

A few more details on the digital side:

Audio is I2S, 48kHz. MCLK is 12.288MHz, SCK is 3.072MHz.

Thanks Abi,

*Can you please confirm the 6s delay is seen at the output of the DAC itself or after I to V converter or after Diff to single ended. I did not see the answer to this question that I asked before.

*Please provide  the spec for  clks (fs, BCK, SCK )  and from plots it is 32bit and 48k sampling rate?

* All 3 plots provided above are identical;  even the time stamp is same to the minute and seconds, Please on the scope monitor and plot 

            1)supply voltage as apposed to the vout settling  ( need to see the 6s in question starts from what point, For example  is this 6s  starts from when supply is stabled and reached its final value,  (show the LRCK and SDIN as well ) 

            2) Reset vs Vout  ( Is  6s starts from the edge of reset toggle or ....)  show the LRCK and SDIN as well 

   3) All clks and data input , I need to be able to see the shift of data wrt BCK and LRCLK ( refer to figure 37 )

   4) a zoom in on VOUT to see how this transition looks like,

Thanks,

Arash 

Hi Arash,

the ramp is visible at the output of the I to V converter. I haven't disconnected the DAC to see if it's present there. I don't have a reason to suspect the I-V converter is ramping.

FS is 48Khz, BCK is 3.072MHZ, MCLK us 12.288MHz, all 50% duty cycle.

32bit, 48KHz sample rate

from the video above, the 6s starts when signal is first visible on the I-V stage.

Here's the turn on timing with the supply, LRCK, DATA, and output of the I-V stage

Here's reset, LRCK, DATA, and I_V output

Here's a zoom of the clock and data with persistence

Here's a zoom in of Vout during the ramping

Hi Brian, the typical  internal delay of the IC (input to output)  is speced  as 38/fs  which is equal to 38/48000= 7.917e-4s, From your second plot, it seems it is about 250ms  which is still too much.

This is a Current DAC and it looks the output  is charging a cap at its output , that is why we wanted to monitor it without any loading to see if the issue is still there.

Also when you put a full scale sinewave, once everything is settled, do you get the expected amplitude of the the sinewave per datasheet?

Regards,

Arash