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Tool/software:
Hi team,
My customer is testing the ADC spec; since their current frequency is high ~24MHz, so close to our part boundary. The tHBCLK and tLBCLK spec get to ~20ns.
They are checking the note(1), that could extend the BCLK high and low spec to 14ns. Could you help understand what does it mean "SDOUT data line is latched on the same BCLK edge polarity as the edge used by the device to transmit SDOUT data." ? How could we know if the set up meet the requirement or not?
Thanks and best regards,
Will
Hi Will,
This is saying that the pulse duration is relaxed to 14ns to allow for faster transitions if transmission of SDOUT and latching of BCLK were to both occur on the rising edge or falling edge. The timing constraints can be relaxed since the edge polarity is synchronized
Hi Daveon,
Thanks for your comments.
For the following 2 sequence, could you help comment which one could be released to 14ns?
Thanks and Best regards,
Will
Hi WIll,
Figure 8-1 is an exampled where the timing can be relaxed. As the data transmission and fsync are all synchronized to the rising edge of BCLK