Hello,
I am trying to use the miniDSP on the AIC3254 codec, but I cannot seem to get any output other than noise from the device. For now, I am trying to use the TMDXMDKDS3254 digital stethoscope frontend with most of the code on the TMS320C5515 EVM base board disabled.
I am using the 12 MHz oscillator on the frontend board as the input to PLL_CLKIN. I suspect there is something wrong with the way I am configuring the codec's clocks and dividers, but I am not sure. I've double checked that all of my I2C commands are reaching the codec as intended.
My I2C configuration for the codec is below. Does anything jump out as immediately wrong? This is my first time directly working with a codec so I would appreciate some help.
...<miniDSP_A and miniDSP_D instructions>...
static reg_value REG_Section_program[] = {
{0,0x00}, //Point to page 0
{1,0x01}, //Reset the codec
{255,0xFE},//Special command to program the miniDSPs' instructions
//********************************* Turn on the miniDSPs ************************************************************
{ 0,0x00},
// # reg[ 0][ 60 (0x3C)] = 0x00 ; Use miniDSP_D for signal processing
{ 0x3C,0x00},
// # reg[ 0][ 61 (0x3D)] = 0x00 ; Use miniDSP_A for signal processing
{ 0x3D,0x00},
// # reg[ 0][ 17 (0x11)] = 0x02 ; 2x Interpolation
{ 0x11,0x02},
// # reg[ 0][ 23 (0x17)] = 0x01 ; 1x Decimation
{ 0x17,0x01},
//
{ 0x0F,0x02},
//
{ 0x10,0x00},
//
{ 0x15,0x02},
//
{ 0x16,0x00},
{ 0,0x08}, //Select page 8
// # reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
{ 0x01,0x04},
{ 0,0x2C}, //Select page 44
// # reg[ 44][ 1] = 0x04 ; adaptive mode for DAC
{ 0x01,0x04},
//********************************* Turn on analog blocks ************************************************************
{0,0x01}, //Point to page 1
{1,0x08}, //Disable crude AVDD generation from DVDD
{2,0x00}, //Enable Analog Blocks
//********************************* CODEC Clock and Dividers ************************************************************
{0,0x00}, //Point to page 0
{0x1B,0x00}, //I2S interface, 16 bit data word length, BLCK and WCLK input from master
//For AIC Slave running off of 768 kHz or 1.536 MHz BCLK supplied by I2S. BCLK and WCLK is set as input to AIC3254(slave)
//{4,0x07}, //PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK
{4,0x03}, //PLL setting: PLLCLK <- MCLK (12Mhz) and CODEC_CLKIN <- PLLCLK
{6,0x04}, //PLL setting: J=4
//{6,0x20}, //PLL setting: J=32
{7,0x00}, //PLL setting: HI_BYTE(D) for D=0x0 (or 0 decimal)
{8,0x00}, //PLL setting: LO_BYTE(D) for D=0x0
{0x1E,0xA0},//BCLK N divider. TODO:see if this can be removed. It shouldn't affect the system since BCLK is supplied to us
//{5,0x94}, //PLL setting: Power up PLL, P=1 and R=4 (for 12 kHz sampling)
{5,0xC1}, //PLL setting, R=1, P=4 (gives PLL_CLK of 12 MHz), power up the PLL
{0x0B,0x88}, //Power up NDAC and set NDAC value to 8 (gives DAC_CLK = 1.5Mhz)
{0x0C,0x81}, //Power up MDAC and set MDAC value to 1 (gives DAC_MODCLK = 1.5 Mhz)
{0x0D,0x00}, //Hi_Byte(DOSR) for DOSR = 125 decimal or 0x007D DAC oversampling (for 12 kHz sampling)
{0x0E,0x7D}, //Lo_Byte(DOSR) for DOSR = 125 decimal or 0x007D
{0x12,0x88}, //Power up NADC and set NADC value to 8 (gives ADC_CLK = 1.5Mhz)
{0x13,0x81}, //Power up MADC and set MADC value to 1 (gives ADC_MODCLK = 1.5Mhz)
{0x14,0x7D}, //AOSR for AOSR = 125 decimal or 0x007D (gives ADC_FS = 12 kHz)
//********************************** Routing and turn on the proper signal blocks ************************************************
{0,0x01}, //Select page 1
{0x0A,0x00},
{0x33,0x40}, //Mic bias
//{0x0C,0x02}, //IN1L routed to HPL through the MAL
//{0x0D,0x02}, //IN1R routed to HPR through the MAR
{0x0C,0x08}, //Left channel DAC reconstruction filter output routed to HPL
{0x0D,0x08}, //Right channel DAC reconstruction filter output routed to HPR
{0,0x00}, //Select page 0
{0x40,0x02}, //Left vol=right vol
{0x41,0x00}, //Left DAC gain to 0dB VOL; Right tracks Left
{0x3F,0xD4}, //Power up left,right data paths and set channel
{0,0x01}, //Select page 1
{0x10,0x0C}, //Unmute HPL , 0dB gain
{0x11,0x0C}, //Unmute HPR , 0dB gain
{9,0x32}, //Power up HPL,HPR, MAL
//{9,0x30}, //Power up HPL, HPR
{0,0x00}, //Select page 0
{255,0xFF}, //Special instruction to do a delay
{0,0x01}, //Select page 1
{0x34,0x20}, //IN2_L to Left MICPGA through 20 kohm (Stereo 1 jack)
{0x37,0x00}, //Don't route IN1R IN2R IN3R and IN2L to the PGA
{0x36,0x02}, //CM_2 (common mode) to LADC_M through 20 kohm
{0x39,0x00}, //Don't route CM1R, IN1L, IN3L, or CM2R to the Right MICPGA
{0x3B,0x05}, //MIC_PGA_L unmute: 2.5dB
{0x3C,0x80}, //Disable MIC_PGA_R
{0,0x00}, //Select page 0
{0x53,0x00}, //Gain Left 0dB
{0x51,0x80}, //Powerup Left ADC
{0x52,0x08}, //Unmute Left and mute Right ADC
{0,0x01} //Select page 1
};
...<rest of file>