SRC4182 / DC level output at mute mode

Here is attachment.

Hi, Sonoki,

What kind of DC voltages are they measuring? 

-d2

Hi Don-san,

I received the waveform of SDOUT at no SDIN, BCKI, LRCKI. Please refer the previous attachment regarding simplified circuit.

Please let me change our questions as below and ask again.

1, The output signal looks like the signal at some DC signal was input though there is no SDIN, BCKI, LRCKI. Is this signal normal?

2, Please let us know why such signal was confirm if it's abnormal.

Best Regards,

Sonoki

Hi, Sonoki,

Do they do a reset at start-up? I wonder if this is causing the problem?

What happens if they unplug the source after the device has been playing audio? It looks from your one plot that there is not a problem then, so I'm suspecting the start-up reset?

From the d/s:

-d2

Don-san,

I found out the problem they care about is a dithering signal on low-order bit. So now I'm requesting them to try to set to the bypass mode to disable dithering and if the pulse on SDOUT they confirmed will be removed. Let me update when I will receive their feedback.

Best Regards,

Sonoki

Hi, Sonoki,

Great news! Let me know how it turns out.

-d2

Hi Don-san,

I have additional information and can clarify what they need to know. Please see below and updated attached file.

Additional information

1. There is no dither signal and pulse on high-order bit when LRCKI and BCLI was input and no SDIN after a reset at start-up.
2. When SDIN, LRCKI and BCLI were input and after that these input was gone to Low (No input and CLK condition), dither signal and pulse on high-order bit were confirmed.
3. After the #2 above, pulse on high-order bit was removed when LRCKI and BCLI were input. This is cause of pop noise in their system, so they need to know how to not output this pulse on high-order bit.

Question

1, Can you clarify how many bits are applied for dither signal? (e.g., Is it applied by  low order 3 or 4 bits)

2, Is following operation normal operation? (Asking about #1 and 2 above)

• There is no dither signal and pulse on high-order bit when LRCKI and BCLI was input and no SDIN after a reset at start-up.
• When SDIN, LRCKI and BCLI were input and after that these input was gone to Low (No input and CLK condition), dither signal and pulse on high-order bit were confirmed.

3, Is following operation normal operation? (Asking about #3 above)

• The pulse on high-order bit was removed when LRCKI and BCLI were input.

4, Can you give us advice to remove the pulse on high-order bit? They need to remove it because this is caused of pop noise in their system when pulse on high-order bit is stopped after LRCKI and BCLI were input. Should they need to set MUTE pin to High at no LRCKI and BCLI condition?

Best Regards,

Sonoki

Hi Don-san,

What's the status of this question? Please let me know if you need more information to comment.

Best Regards,

Sonoki

Hi, Sonoki,

Unfortunately, the device requires clocks in order to start-up properly. This is what is causing the issue - the part is in an unknown state until the clocks are supplied.

So, they somehow need to figure out how to keep the part in RESET until valid clocks are available. In our designs, we usually use something like the SPDIF lock signal from the DIR9001 to accomplish this, for example.

-d2

Hi Don-san,

Thank you for your response. Today I provided a description of cause of this issue you commented. And also I suggested to keep the part in RESET by using /RST. However they can not change their design because they already finished the evaluation of pre-production. They need to judge if they can accept this issue so can you please give your comments for following questions?

1, 

Can you clarify how many bits are applied for dither signal? (e.g., Is it applied by  low order 3 or 4 bits)

2,

Can you recommend to keep device in mute instead of reset though you recommend to keep the part in RESET until valid clocks are available?

3,

Can you clarify the maximum level of unknown  high-order bit signal? They confirmed that the unknown signal level at "SDIN, LRCKI, and BCKI goes Low after full-bit SDIN" is higher than at "SDIN, LRCKI, and BCKI goes Low after no SDIN". They hope to know the worst case because they may not add changing to measures to suppress this unknown signal.

I have to inform customer of comments for these questions. so please give your response by 12:00 PM on Thursday JST.

Best Regards,

Sonoki

Hi Don-san,

Today I had a meeting with customer and confirmed detailed information. I need to correct the information so please let me explain the situation at customer side.
Please also refer waveform in attached.

[Status and schedule]
Start mass-production from end of May.
They can not revise the hard and soft ware from now.

[ Phenomenon]
They confirmed repeatable signal in addition to dithered signal at no SDIN and following specified condition. (It has been repeatable signal, not DC level output, so please let me correct.)

- Stop the SDIN to SRC4182
- After that stop the LRCKI and BCKI to SRC4182

[Customer's supposition]
This signal looks like a last part of signal to SDIN.
Then they suspect that SRC4182 output the signal periodically with no SDIN, and this output signal is the same with signal which is input to SDIN when LRCKI and BCKI are stopped.

[Question for TI (Priority order)]
1, Please comment for the phenomenon at customer side and their supposition
2, You commented that "RESET until valid clocks are available", then how long time can they keep /RST to Low after valid clocks are available?
They need to find corrective action to apply it after mass-production. That is the reason why they are asking this.
3, You commented that "the device requires clocks in order to start-up properly", then we understand that the clocks here means LRCKI and BCKI, not RCKI. Is it correct?
4, Can you clarify how many bits are applied for dither signal? (e.g., Is it applied by low order 3 or 4 bits)
They need to know the output level from SRC4182 at no high-order bit signal (Good case in attached). That is the reason why they are asking this.

Your kind response will be appreciated.

Best Regards,

Sonoki

Hi, Sonoki,

It is going to take me some time to gather this information. We will get it as rapidly as possible.

-d2

Hi, Don-san,

Thank you for your quick response!

I'd like to know your progress until today your time.

Your understanding will be appreciated.

Best Regards,

Sonoki

Hi Don-san,

Today I talked with TIJ person and we assumed that this repeatable signal is the part of expected output signal due to group delay, not pop noise or unknown noise. I asked customer already that the analog signal on speaker out (see attached) is the same signal with input signal.

Can you please give your comment if this our updated supposition is correct?

Best Regards,

Sonoki

Hi Don-san,

Can you give your update until today? Please give your comments through TIJ person internally if you need.

Best Regards,

Sonoki

Hi Don-san,

Please give your asnwer for this post though I asked questions in previous post.

1, we assumed that this repeatable signal is the part of expected output signal due to group delay, not pop noise or unknown noise. I asked customer already that the analog signal on speaker out (see attached) is the same signal with input signal. Can you please give your comment if this our updated supposition is correct?

2, You commented that "RESET until valid clocks are available", then how long time can they keep /RST to Low after valid clocks are available?
They need to find corrective action to apply it after mass-production. That is the reason why they are asking this.

3, You commented that "the device requires clocks in order to start-up properly", then we understand that the clocks here means LRCKI and BCKI, not RCKI. Is it correct?

4, Can you clarify how many bits are applied for dither signal? (e.g., Is it applied by low order 3 or 4 bits)
They need to know the output level from SRC4182 at no high-order bit signal (like Good case in attached). That is the reason why they are asking this.

Best Regards,

Sonoki

LRCKI and LRCKO are required to be active for SRC4182 operation. MUTE has to be forced to high when LRCKI stops, otherwise you may observe unpredictable output. The external MUTE has to be or’ed with RDYB from SRC4182 to drive the MUTE pin.

Hi Hartl-san,

Thank you for your response. I understand that the MUTE pin should be kept Low by external signal when LRCKI and LRCKO stops. And as you understand that our customer use MUTE pin with tying to /RDY pin, so I prepared the proposal for oring external signal and /RDY output as attached. Can you accept this proposal?

Your quick response will be appreciated.

Best Regards,

Sonoki

Hi Don-san,

We need to explain the cause of this phenomenon to close this question. I prepared the draft with TIJ person, so can you check it and give your comments if it is needed to edit.

SRC4182 has interpolation filter and it buffer the data. The length of the data is set by group delay. If the SDIN and BCKI are lost at the same time, the data is remained in the buffer.
After the BCKI is lost, the data in buffer is not cleared and the remained data is output continuously because the BCKI is not provided and so the data is not updated.
So the data in buffer is cleared and no data is output if the SDIN is zero data at BCKI is lost.
This output of buffered data can be stopped by muting SRC4182.
This is assumed operation, so any damage or quality issue is not concerned.

Best Regards,

Sonoki

Hi Don-san,

Can you give your comment for this post?

Best Regards,

Sonoki

1. When BCKI and/or LRCKI stop toggling, the input audio interface stops operating. As result, the audio data in the buffer are not updated. The ASRC will continuously play the old data in the buffer repeatedly when the MUTE is low.
2. When LRCKI stops, RDYB may stuck at low if it has been low. If RDYB is connected to MUTE pin directly, the ASRC output will behave as described in item 1.
3. When MUTE is high, the ASRC output will be ramping down to zero;
4. Based on 1,2 and 3, an external MUTE signal is needed and set high when BCKI or LRCKI stops. It should be set low when BCKI and LRCKI run normally. This external MUTE should be logic or’ed with RDYB to drive MUTE pin.