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TAS5414C-Q1: TAS5414C Slave initialization.

Artem Gromak
Prodigy 50 points
Part Number: TAS5414C-Q1
Other Parts Discussed in Thread: TAS5414

Hi.

My scheme have  two TAS5414 chip. The first TAS5414 -  the master (i2c-address 0xD8 / 0xD9). Second - slave (i2c-address - 0xDA / 0xDB).
Initialization I2C master after leaving standby:
1 .Read register 0
2. Read register 1
3. Write register 0x09 0xF0 - Current limit level 2 for all channels, thermal foldback is active
4. Write in the register 0x0A 0x4E - Send sync pulse from OSC_SYNC pin,  report clip and OTW, fS = 357 kHz

What is better to choose the frequency (357 kHz or 417 kHz or 500 kHz)?

5. Write register 0x0B 0xC0 - master clock mode, enable clock output on OSC_SYNC pin

Initialize slave:
1 .Read register 0
2. Read register 1
3. Write register 0x0B 0x10 - Enable tweeter-detect mode, Enable slave mode


Are there enough such initialization, or must to add something else?

Thanks!

  • 0
    TI__Guru 57800 points

    Hi, Artem,

    My colleague will take a look to your questions, as he is traveling now, the response might be delayed. Sorry for the inconvenience.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0
    TI__Mastermind 34305 points

    Artem,

    Sorry for the delay.  I am on business travel.

    There is no need to write to register 0x09.  The default value is 0xF0

    Step 4 should be different.   send to 0x0A a value of 0x04.  (do not send sync pulse)

    The frequency does not matter.  The slave will track the master.

    The two should be synchronized at this point.

  • 0 in reply to Gregg Scott
    TI__Mastermind 34305 points
    Artem,
    I forgot to add the sync pulse sequence. This will align the PWM Fs phase of channel 1 on the slave t the PWM Fs phase of channel 2.
    Bit D6 controls a feature to send a synchronization pulse on the OSC_SYNC pin. All slaves must have this bit set to "1" to prepare it to receive the pulse, then the master is set to "1" to send the pulse. After completion the bits will be cleared and all devices will be Fs phase synchronized.
    Perform this after step 3 on the slave routine.
  • 0 in reply to Gregg Scott
    Prodigy 50 points

    Hi, Gregg. Thanks for answer.

    So the initialization sequence is as follows:

    1 .Read from master register 0
    2. Read from master register 1

    3. Write to master in the register 0x0A 0x40

    4 .Read from slave register 0
    5. Read from slave register 1
    6. Write to slave  register 0x0B 0x10 - Enable tweeter-detect mode, Enable slave mode

    7. Write to slave register 0x0A of 0x40 - D6 = 1

    8. Write to master register 0x0A of 0x40 - D6 = 1 

    10. Read from slave register 0x0A while D6 are not cleared

    11. Read from master register 0x0A while D6 are not cleared

    That's right?
    Thank you

  • 0 in reply to Artem Gromak
    TI__Mastermind 34305 points

    Artem,

    Upon a quick review the master is never set up to have the clock on the OSC_SYNC pin. 

    I will review this and reply when I return to Dallas.